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    Seat heater
    1.
    发明授权
    Seat heater 有权
    座椅加热器

    公开(公告)号：US09012812B2

    公开(公告)日：2015-04-21

    申请号：US13575209

    申请日：2011-01-31

    申请人： Kenji Anzai ,  Hiroki Nagayama ,  Hajime Oi

    发明人： Kenji Anzai ,  Hiroki Nagayama ,  Hajime Oi

    IPC分类号： H05B1/02 ,  H05B3/00 ,  H05B11/00 ,  B60L1/02 ,  B60N2/56

    CPC分类号： B60N2/5685

    摘要： A seat heater (10) that is provided on a seat (1) including a seat cushion (2) and a seat back (3) includes a first heating element (12U) provided in an upper section (3Lu) of a backrest (3L) in the seat back (3) and a second heating element (12L) provided in a lower section (3Ll) of the backrest (3L) in the seat back (3). In addition, a heat generation density of the first heating element (12U) is lower than a heat generation density of the second heating element (12L).

    摘要翻译： 设置在包括座垫（2）和座椅靠背（3）的座椅（1）上的座椅加热器（10）包括设置在靠背（3L）的上部（3Lu）中的第一加热元件（12U） ）和设置在座椅靠背（3）中的靠背（3L）的下部（3L）中的第二加热元件（12L）。 此外，第一加热元件（12U）的发热密度低于第二加热元件（12L）的发热密度。

    SEAT HEATER
    2.
    发明申请
    SEAT HEATER 有权
    座椅加热器

    公开(公告)号：US20120292301A1

    公开(公告)日：2012-11-22

    申请号：US13575209

    申请日：2011-01-31

    申请人： Kenji Anzai ,  Hiroki Nagayama ,  Hajime Oi

    发明人： Kenji Anzai ,  Hiroki Nagayama ,  Hajime Oi

    IPC分类号： H05B1/00

    CPC分类号： B60N2/5685

    摘要： A seat heater (10) that is provided on a seat (1) including a seat cushion (2) and a seat back (3) includes a first heating element (12U) provided in an upper section (3Lu) of a backrest (3L) in the seat back (3) and a second heating element (12L) provided in a lower section (3Ll) of the backrest (3L) in the seat back (3). In addition, a heat generation density of the first heating element (12U) is lower than a heat generation density of the second heating element (12L).

    摘要翻译： 设置在包括座垫（2）和座椅靠背（3）的座椅（1）上的座椅加热器（10）包括设置在靠背（3L）的上部（3Lu）中的第一加热元件（12U） ）和设置在座椅靠背（3）中的靠背（3L）的下部（3L）中的第二加热元件（12L）。 此外，第一加热元件（12U）的发热密度低于第二加热元件（12L）的发热密度。

    Electrically alterable n-bit per cell non-volatile memory with reference cells
    3.
    发明授权
    Electrically alterable n-bit per cell non-volatile memory with reference cells 失效
    具有参考单元的每个单元非易失性存储器的电可变n位

    公开(公告)号：US5596527A

    公开(公告)日：1997-01-21

    申请号：US387562

    申请日：1995-02-13

    申请人： Yugo Tomioka ,  Shoichi Iwasa ,  Yasuo Sato ,  Toshio Wada ,  Kenji Anzai

    发明人： Yugo Tomioka ,  Shoichi Iwasa ,  Yasuo Sato ,  Toshio Wada ,  Kenji Anzai

    IPC分类号： G11C11/56 ,  G11C16/28 ,  G11C11/34

    CPC分类号： G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.

    摘要翻译： 一种具有包括多个存储单元的存储单元阵列的电可更改的非易失性存储器，每个存储单元包括具有多个不同阈值电压中选择的一个的晶体管; 包括至少一组参考单元的参考单元阵列，所述组中的每个参考单元被设置为不同的阈值电压; 用于选择所述存储器单元之一的选择电路; 以及比较电路，用于将从所选择的存储单元读出的存储器电流与从参考单元读出的参考电流中的每一个依次按照为参考单元设置的阈值电压的电平顺序依次进行比较，从而根据 进行比较。

    Semiconductor memory device having memory cells including transistors and capacitors
    4.
    发明授权
    Semiconductor memory device having memory cells including transistors and capacitors 失效
    具有存储单元的半导体存储器件包括晶体管和电容

    公开(公告)号：US5410503A

    公开(公告)日：1995-04-25

    申请号：US161537

    申请日：1993-12-06

    申请人： Kenji Anzai

    发明人： Kenji Anzai

    IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  G11C11/24

    CPC分类号： H01L27/10852 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L27/10829 ,  H01L28/40 ,  H01L29/945 ,  Y10S148/014

    摘要： A semiconductor memory device having memory cells including a transistor and a trench type capacitor which are formed on a semiconductor substrate to cooperate with each other to store information. The device includes a trench having a bottom made of a first insulator disposed on the semiconductor substrate and a sidewall made of an epitaxial semiconductor layer which is epitaxially grown on the semiconductor substrate in a substantially vertical direction around the first insulator. The capacitor comprises an impurity diffused layer formed on the sidewall of the trench, a second insulator layer formed over thee impurity diffused layer, and a conductive layer opposite of the impurity diffused layer via the second insulator layer, with the transistor formed on the epitaxial semiconductor layer.

    摘要翻译： 一种半导体存储器件，具有包含晶体管和沟槽型电容器的存储单元，所述晶体管和沟槽型电容器形成在半导体衬底上以相互配合以存储信息。 该器件包括：沟槽，其具有由设置在半导体衬底上的第一绝缘体制成的底部和由外延半导体层制成的侧壁，该外延半导体层沿着围绕第一绝缘体的大致垂直方向在半导体衬底上外延生长。 电容器包括形成在沟槽的侧壁上的杂质扩散层，形成在杂质扩散层上的第二绝缘体层，以及经由第二绝缘体层与杂质扩散层相反的导电层，晶体管形成在外延半导体 层。

    Process for producing a semiconductor memory device having memory cells including transistors and capacitors
    6.
    发明授权
    Process for producing a semiconductor memory device having memory cells including transistors and capacitors 失效
    具有包括晶体管和电容器的存储单元的半导体存储器件的制造方法

    公开(公告)号：US5292679A

    公开(公告)日：1994-03-08

    申请号：US49306

    申请日：1993-04-21

    申请人： Kenji Anzai

    发明人： Kenji Anzai

    IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L21/70

    CPC分类号： H01L27/10852 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L27/10829 ,  H01L28/40 ,  H01L29/945 ,  Y10S148/014

    摘要： A semiconductor memory device having an excellent data holding characteristics because of a small leak current from a trench and a process for producing the same are disclosed. An SiO.sub.2 film 12 having an appropriate pattern is formed on a P type silicon substrate 11. Trenches 14 are relatively formed on the SiO.sub.2 film 12 by selectively growing a P type epitaxial layer 13 on the silicon substrate 11 using the SiO.sub.2 film 12 as a mask. An N type layer 23 acting as an electrode of a capacitor 27 is formed on the inner wall of the trench 14 by the oblique ion implantation of impurities 22 thereto. A polycrystalline silicon film 25 acting as an opposite electrode of the capacitor 27 is formed on an ONO film 24 so that the ONO film 24 is disposed between the polysilicon film 25 and the SiO.sub.2 film. The semiconductor memory device which is produced by this method without etching to form the trenches 14 has a fewer crystal defects in the epitaxial layer 13 around the trenches 14. Accordingly, the data holding characteristics are improved since the leak current from the trenches 14 becomes less. As a result of this, higher density integration is possible since the device can be made with less capacitance of capacitors.

    摘要翻译： 公开了一种具有优良的数据保存特性的半导体存储器件，因为来自沟槽的泄漏电流很小，并且制造过程也是如此。 在P型硅衬底11上形成具有适当图案的SiO 2膜12.通过使用SiO 2膜12作为掩模，在硅衬底11上选择性地生长P型外延层13，在SiO 2膜12上相对形成沟槽14 。 作为电容器27的电极的N型层23通过倾斜离子注入杂质22而形成在沟槽14的内壁上。 在ONO膜24上形成充当电容器27的相对电极的多晶硅膜25，使得ONO膜24设置在多晶硅膜25和SiO 2膜之间。 通过该方法制造的半导体存储器件，不经蚀刻形成沟槽14，在沟槽14周围的外延层13中具有较少的晶体缺陷。因此，数据保持特性得到改善，因为来自沟槽14的泄漏电流变小 。 结果是，由于可以用较小的电容器电容来制造更高密度的集成。

    Non-volatile semiconductor memory cell capable of storing more than two different data and method of using the same
    8.
    发明授权
    Non-volatile semiconductor memory cell capable of storing more than two different data and method of using the same 失效
    能够存储两种不同数据的非易失性半导体存储器单元及其使用方法

    公开(公告)号：US5424978A

    公开(公告)日：1995-06-13

    申请号：US212737

    申请日：1994-03-14

    申请人： Toshio Wada ,  Kenji Anzai ,  Shoichi Iwasa ,  Yasuo Sato ,  Yuichi Egawa

    发明人： Toshio Wada ,  Kenji Anzai ,  Shoichi Iwasa ,  Yasuo Sato ,  Yuichi Egawa

    IPC分类号： G11C11/56 ,  G11C11/34

    CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： A non-volatile semiconductor memory device capable of selectively storing one of at least three different data comprises a memory array including a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source, a circuit for producing a stepped voltage whose level is varied stepwise to a number of different levels corresponding to a number of data to be stored, a circuit for producing a pulse voltage having a predetermined voltage level and a predetermined pulse width, and a circuit for selecting one of the plurality of memory cells, wherein during storing of the at least three different data the stepped voltage and the pulse voltage are applied to the control gate and the drain of the selected memory cell, respectively, while a timing of application of the pulse voltage to the drain is controlled relative to a timing of application of the stepped voltage to the control gate, depending on which of the at least three different data is to be stored into the selected memory cell.

    摘要翻译： 能够选择性地存储至少三种不同数据中的一种的非易失性半导体存储器件包括：存储器阵列，其包括多个存储单元，每个存储单元具有控制栅极，浮置栅极，漏极和源极， 阶梯电压，其电平逐步变化为对应于要存储的数据的数量的不同电平的数量，用于产生具有预定电压电平和预定脉冲宽度的脉冲电压的电路，以及用于选择 多个存储单元，其中在存储所述至少三个不同数据期间，分阶段电压和脉冲电压分别施加到所选择的存储单元的控制栅极和漏极，同时将脉冲电压施加到 相对于将步进电压施加到控制栅极的时序来控制漏极，这取决于至少三个不同数据中的哪一个将被存储到第 e选择的存储单元。

    Packet relaying apparatus
    9.
    发明申请
    Packet relaying apparatus 审中-公开
    分组中继装置

    公开(公告)号：US20070230435A1

    公开(公告)日：2007-10-04

    申请号：US11726855

    申请日：2007-03-23

    申请人： Kenji Anzai

    发明人： Kenji Anzai

    IPC分类号： H04L12/28

    CPC分类号： H04L47/801 ,  H04L47/15 ,  H04L47/70 ,  H04L47/748 ,  H04L49/205

    摘要： A packet relaying apparatus which relays packets with a guaranteed bandwidth between terminals is comprised of a session control information analyzing section which identifies a required bandwidth required for a session to be established between the terminals by analyzing session control information contained in packets of control session protocols between the terminals, and a bandwidth correction section which corrects the identified required bandwidth based on the header size information of the packets, in order to guarantee the corrected bandwidth for the packets relating to the session.

    摘要翻译： 中继具有终端之间保证带宽的分组的分组中继装置由会话控制信息分析部分组成，会话控制信息分析部分通过分析包含在控制会话协议的分组中的会话控制信息来识别在终端之间建立的会话所需的带宽 终端和带宽校正部分，用于基于分组的报头大小信息来校正所识别的所需带宽，以便保证与会话有关的分组的校正带宽。