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1.发明授权Timing vernier architecture for generating high speed, high accuracy timing edges 有权定时游标架构，用于产生高速，高精度的时序边缘公开(公告)号：US06774694B1
公开(公告)日：2004-08-10
申请号：US10328637
申请日：2002-12-24
IPC分类号： H03H1126
CPC分类号： H03L7/0812 , H03K5/133 , H03K5/1508 , H03L7/07
摘要： A timing vernier applies a pair of stable bias voltages to intermediate points of an impedance string to establish reliable and calibratable delay cell biases for a fine multiplexer. A coarse input multiplexer is switched to a new timing signal substantially immediately after passing a prior valid timing signal to maximize the time prior to each valid output that the waveform is independent of the prior delay pattern. Logic circuitry is provided for three different phase differential regimes between successive timing signals to ensure that invalid output signals separated by less than a clock period are not produced. Mask commands are inserted into a series of timing control commands to equalize the average rates of writing and reading out the timing control commands with the mask commands skipped at readout.
摘要翻译： 定时游标器将一对稳定的偏置电压施加到阻抗串的中间点，以为精细多路复用器建立可靠和可校准的延迟单元偏移。 粗略输入多路复用器在通过先前的有效定时信号之后基本上立即被切换到新的定时信号，以使每个有效输出之前的时间最大化波形独立于先前的延迟模式。 为连续定时信号之间的三个不同的相位差方案提供逻辑电路，以确保不产生分开不到时钟周期的无效输出信号。 掩码命令被插入到一系列定时控制命令中，以平均写入速率和读出定时控制命令，并在读出时跳过掩码命令。
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2.发明授权公开(公告)号：US06265901B1
公开(公告)日：2001-07-24
申请号：US09448121
申请日：1999-11-24
IPC分类号： H03K19086
CPC分类号： H03M7/22
摘要： A high speed, multiple input restrictive OR circuit with fully differential inputs and output is used in applications in which only one input can be active at a time. N differential voltage inputs are converted into N corresponding differential current signals of unit current values. The current signals corresponding to active complement input signals are summed together, with a compensation current equal to (N−1) current units subtracted from the total. The resulting compensated complement currents together with any active input current form a single differential current that indicates the logic state at the input. This differential current is preferably converted to a buffered output differential voltage in an output stage. For high accuracy applications, a common unit reference current is used to generate both a scaled compensation current and unit input stage source currents.
摘要翻译： 具有全差分输入和输出的高速，多输入限制OR电路用于一次只能有一个输入有效的应用中。 N个差分电压输入转换为单位电流值的N个相应的差分电流信号。 与有效补码输入信号对应的电流信号相加在一起，补偿电流等于从总数减去的（N-1）个当前单位。 所产生的补偿补偿电流与任何有源输入电流一起形成单个差分电流，指示输入端的逻辑状态。 该差分电流优选地在输出级转换为缓冲输出差分电压。 对于高精度应用，公共单位参考电流用于产生标定的补偿电流和单位输入级源电流。
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公开(公告)号：US5150386A
公开(公告)日：1992-09-22
申请号：US308326
申请日：1989-02-09
CPC分类号： G06F5/10 , H03L7/085 , H03L7/0991 , H03L7/181 , H04J3/0626 , G06F2205/061
摘要： A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.
摘要翻译： 时钟倍增器/抖动衰减器电路提供稳定的时钟，其是外部数字数据流的平均频率的多个频率。 外部数据以其自己的时钟速率写入FIFO的连续存储单元，并以由分频稳定时钟形成的内部时钟信号的速率读出FIFO。 以周期性的时间间隔确定要写入的单元和读出的单元的相对位置，并且这些相对位置用于调整产生稳定时钟的内部振荡器的频率。 数字数据流上的瞬时抖动被FIFO吸收。
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4.发明授权公开(公告)号：US06242959B1
公开(公告)日：2001-06-05
申请号：US09453148
申请日：1999-12-02
申请人： Kenneth J. Stern
发明人： Kenneth J. Stern
IPC分类号： H03H1126
CPC分类号： H03K5/131 , H03K2005/0013 , H03K2005/00143
摘要： One or more main programmed delay circuits (PDCs) are compensated to provide constant delays despite variations in environmental factors, such as temperature and power supply, by means of a dummy PDC that emulates the main PDCs in environmental sensitivity. While the main PDCs have dynamically changing programmed inputs, the dummy PDC has a constant programmed input. Changes in the dummy PDC's delay due to environmental changes are monitored and a correction signal is applied to the dummy PDC to maintain its delay substantially constant, with the same correction provided to the main PDCs to correct for the same changes in the delay of these circuits. The dummy PDC is preferably initially calibrated so that its fixed delay period coincides with an integer number of clock periods. Both the main and dummy PDCs preferably produce respective delays equal to the linear sum of a programmed delay and their correction delays.
摘要翻译： 补偿一个或多个主要编程延迟电路（PDC），以通过模拟环境敏感度的主要PDC的虚拟PDC来改变环境因素（例如温度和电源）的变化的恒定延迟。 虽然主要的PDC具有动态变化的编程输入，但虚拟PDC具有恒定的编程输入。 监视由于环境变化引起的虚拟PDC延迟的变化，并且将校正信号施加到虚拟PDC以保持其延迟基本上恒定，同时向主PDC提供相同的校正以校正这些电路的延迟的相同变化 。 虚拟PDC优选地被初始校准，使得其固定延迟周期与整数个时钟周期一致。 主PDM和伪PDC都优选地产生等于编程延迟的线性和及其校正延迟的相应延迟。
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公开(公告)号：US4988954A
公开(公告)日：1991-01-29
申请号：US345320
申请日：1989-04-28
申请人： Kenneth J. Stern , Stephen F. Bily
发明人： Kenneth J. Stern , Stephen F. Bily
CPC分类号： H03F3/3022 , H03F1/02 , H03F1/0261 , H03F3/265 , H03F3/3001
摘要： A linear power amplifier having differential push-pull outputs, in which each output consists of an upper and a lower output transistor, includes cross-coupling transistors coupled between the gate of each of the output transistors and a reference voltage such that when the cross-coupled transistor is made conductive, it acts to turn off its associated output transistor. Each of the cross-coupled transistors is controlled by the voltage at the gate of the corresponding output transistor at the other of the differential outputs. Thus, the cross-coupling transistors insure that only one of the upper output transistors is on at one time and only one of the lower output transistors is on at any one time. These cross-coupling transistors operate in conjection with output stage shutoff circuitry to control the current wasted in the output stages of the linear power amplifier by ensuring that the output transistors at each output are not both conducting a significant amount of current at any one time. The output stage shutoff circuitry is activated by an external signal which is active when the differential input voltage to the amplifier is zero. During this time the output stage shutoff circuitry isolates the output transistors from the input stages, and forces the output transistors to be nonconductive. The cross-coupled control technique is also applied to single output stages in which cross-coupling transistors cause their respective output transistor to turn off when the other output transistor is conducting significant current.
摘要翻译： 具有差分推挽输出的线性功率放大器，其中每个输出由上部和下部输出晶体管组成，包括耦合在每个输出晶体管的栅极之间的交叉耦合晶体管和参考电压， 耦合晶体管导通，它用于关断其相关的输出晶体管。 每个交叉耦合晶体管由在另一个差分输出处的相应输出晶体管的栅极处的电压来控制。 因此，交叉耦合晶体管确保只有一个上部输出晶体管同时导通，并且只有一个下部输出晶体管在任何一个时间导通。 这些交叉耦合晶体管与输出级截止电路结合起来，通过确保每个输出端的输出晶体管在任何一个时间都不会同时导通大量的电流来控制浪费在线性功率放大器的输出级中的电流。 输出级关断电路由外部信号激活，外部信号在放大器的差分输入电压为零时有效。 在此期间，输出级关断电路将输出晶体管与输入级隔离，并迫使输出晶体管不导通。 交叉耦合控制技术也适用于单输出级，其中交叉耦合晶体管使其相应的输出晶体管在另一输出晶体管导通有效电流时截止。
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公开(公告)号：US4941156A
公开(公告)日：1990-07-10
申请号：US327027
申请日：1989-03-22
申请人： Kenneth J. Stern , John A. Beck
发明人： Kenneth J. Stern , John A. Beck
CPC分类号： G06F5/10 , H03L7/085 , H03L7/0991 , H03L7/181 , H04J3/0626 , G06F2205/061
摘要： A jitter attenuation circuit includes a FIFO data register (10) which is operable to receive data that is synchronized with a Write clock output therefrom synchronized with a Read clock. The data is written to the FIFO register (10) from a location determined by a Write pointer (12). The data is read out from the FIFO register (10) from a location determined by a Read pointer (14) which is clocked by a Read clock. The Read clock is synchronized with the Write clock by a phase lock loop (24). The phase lock loop (24) has a phase detector (26) which is operable to accrue phase error over intervals of 2.pi. radians such that the phase lock loop (24) virtually never loses lock as a result of phase jitter on the Write clock. The phase lock loop (24) has contained therein a digitally controlled linear oscillator (28) wherein the phase detector (26) provides a quantized output to incrementally step the digitally controlled oscillator (28) up or down in frequency to track the Write clock while attenuating jitter thereon.
摘要翻译： 抖动衰减电路包括FIFO数据寄存器（10），FIFO数据寄存器（10）可操作以接收与读时钟同步的写时钟输出同步的数据。 从由写指针（12）确定的位置将数据写入FIFO寄存器（10）。 数据从FIFO寄存器（10）从由读取时钟定时的读指针（14）确定的位置读出。 读时钟通过锁相环与写时钟同步（24）。 锁相环（24）具有相位检测器（26），该相位检测器可操作以在2个π弧度的间隔上产生相位误差，使得由于写时钟上的相位抖动，锁相环（24）实际上不会失去锁定 。 锁相环（24）中包含数字控制的线性振荡器（28），其中相位检测器（26）提供量化的输出，以频率递增地步进数字控制的振荡器（28）以跟踪写时钟，同时 衰减抖动。
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公开(公告)号：US06429712B1
公开(公告)日：2002-08-06
申请号：US09941875
申请日：2001-08-29
申请人： Thomas A. Gaiser , Kenneth J. Stern , Farhad Vazehgoo , Vincenzo DiTommaso , William L. Walter , Edward B. Hilton
发明人： Thomas A. Gaiser , Kenneth J. Stern , Farhad Vazehgoo , Vincenzo DiTommaso , William L. Walter , Edward B. Hilton
IPC分类号： H03K3037
CPC分类号： H03K3/012 , H03K3/037 , H03K17/603 , H03K17/6264
摘要： A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.
摘要翻译： 精确的SET-RESET逻辑电路和操作方法将锁存功能与产生逻辑输出的关键信号路径分开。 在特定实现中，逻辑电路包括分别由SET和RESET输入控制的两个差分开关对，以及由锁存电路的输出控制的差分对的各个使能电路。 SET和RESET差分开关对响应快于锁存电路以改变输入SET-RESET状态。 最初通过建立第一个当前路径来产生逻辑输出。 差分开关和使能电路响应于新的逻辑输入，然后通过不同的电流路径锁存。
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公开(公告)号：US06326828B1
公开(公告)日：2001-12-04
申请号：US09456748
申请日：1999-12-07
申请人： Thomas A. Gaiser , Kenneth J. Stern , Farhad Vazehgoo , Vincenzo DiTommaso , William L. Walter , Edward B. Hilton
发明人： Thomas A. Gaiser , Kenneth J. Stern , Farhad Vazehgoo , Vincenzo DiTommaso , William L. Walter , Edward B. Hilton
IPC分类号： H03K3037
CPC分类号： H03K3/012 , H03K3/037 , H03K17/603 , H03K17/6264
摘要： A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.
摘要翻译： 精确的SET-RESET逻辑电路和操作方法将锁存功能与产生逻辑输出的关键信号路径分开。 在特定实现中，逻辑电路包括分别由SET和RESET输入控制的两个差分开关对，以及由锁存电路的输出控制的差分对的各个使能电路。 SET和RESET差分开关对响应快于锁存电路以改变输入SET-RESET状态。 最初通过建立通过差分开关和使能电路的第一电流路径响应于新的逻辑输入而产生逻辑输出，然后通过不同的电流路径锁存。
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公开(公告)号：US4805198A
公开(公告)日：1989-02-14
申请号：US51985
申请日：1987-05-19
CPC分类号： G06F5/10 , H03L7/085 , H03L7/0991 , H03L7/181 , H04J3/0626 , G06F2205/061
摘要： A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.
摘要翻译： 时钟倍增器/抖动衰减器电路提供稳定的时钟，其是外部数字数据流的平均频率的多个频率。 外部数据以其自己的时钟速率写入FIFO的连续存储单元，并以由分频稳定时钟形成的内部时钟信号的速率读出FIFO。 以周期性的时间间隔确定要写入的单元和读出的单元的相对位置，并且这些相对位置用于调整产生稳定时钟的内部振荡器的频率。 数字数据流上的瞬时抖动被FIFO吸收。
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