公开(公告)号：US5759360A

公开(公告)日：1998-06-02

申请号：US402676

申请日：1995-03-13

申请人： Kenny King-Tai Ngan ,  Jaim Nulman

发明人： Kenny King-Tai Ngan ,  Jaim Nulman

IPC分类号： H01L21/302 ,  B08B7/00 ,  C23C14/02 ,  C23C16/02 ,  H01L21/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3065 ,  C23C14/34

CPC分类号： H01L21/02046 ,  B08B7/0035 ,  C23C14/022 ,  C23C16/0245 ,  H01L21/67069

摘要： A method of precleaning a silicon wafer to remove a layer of native silicon oxide thereon comprising adding a mixture of argon and oxygen to a plasma etch chamber including a wafer to be cleaned mounted on a cathode in said chamber, while maintaining the pressure in the chamber below about 3 millitorr. The oxygen is added to react with silicon atoms in the plasma but not with silicon atoms of the single crystal silicon wafer. The presence of oxygen in the plasma at low pressure ensures steady plasma generation and uniform etching across the wafer.

摘要翻译： 一种预硅化硅晶片以除去其上的天然氧化硅层的方法，其中包括将氩和氧的混合物添加到等离子体蚀刻室中，所述等离子体蚀刻室包括安装在所述室中的阴极上的待清洁晶片，同时保持室内的压力 低于约3毫托。 添加氧以与等离子体中的硅原子反应，但不与单晶硅晶片的硅原子反应。 在低压下在等离子体中存在氧气确保稳定的等离子体产生和跨晶片的均匀蚀刻。

公开(公告)号：US20060029489A1

公开(公告)日：2006-02-09

申请号：US11248375

申请日：2005-10-11

申请人： Jaim Nulman ,  Nissim Sidi

发明人： Jaim Nulman ,  Nissim Sidi

IPC分类号： B65H1/00

CPC分类号： H01L21/67769 ,  H01L21/67028 ,  H01L21/67271 ,  H01L21/68707 ,  Y10S414/139 ,  Y10S414/14

摘要： A cassette stocker includes a plurality of cassette storage shelves positioned adjacent a cleanroom wall and vertically disposed relative to a plurality of cassette docking stations, and a cassette mover to carry a cassette between the shelves and the docking stations. An interstation transfer apparatus includes a support beam and a transfer arm adapted to carry a cassette between processing stations.

公开(公告)号：US06572321B1

公开(公告)日：2003-06-03

申请号：US09684142

申请日：2000-10-05

申请人： Jaim Nulman

发明人： Jaim Nulman

IPC分类号： B65G1133

CPC分类号： H01L21/67772 ,  H01L21/67715 ,  H01L21/67736 ,  Y10S414/14

摘要： A loader conveyor adapted so as to receive a wafer carrier from a transfer conveyor and adapted to terminate at an intersection with a processing system, is provided. Thus, the need for a front-end loader robot may be eliminated.

摘要翻译： 提供一种装载机输送机，其适于从传送输送机接收晶片载体并且适于终止于与处理系统的交点处。 因此，可以消除对前端装载机器人的需要。

公开(公告)号：US06171455B2

公开(公告)日：2001-01-09

申请号：US09419712

申请日：1999-10-14

申请人： Vikram Pavate ,  Keith J. Hansen ,  Glen Mori ,  Murali Narasimhan ,  Seshadri Ramaswami ,  Jaim Nulman

发明人： Vikram Pavate ,  Keith J. Hansen ,  Glen Mori ,  Murali Narasimhan ,  Seshadri Ramaswami ,  Jaim Nulman

IPC分类号： C23C1434

CPC分类号： C23C14/3414 ,  Y10S29/002 ,  Y10S29/005 ,  Y10T29/49988

摘要： Improved targets for use in DC_magnetron sputtering of aluminum or like metals are disclosed for forming metallization films having low defect densities. Methods for manufacturing and using such targets are also disclosed. Conductivity anomalies such as those composed of metal oxide inclusions can induce arcing between the target surface and the plasma. The arcing can lead to production of excessive deposition material in the form of splats or blobs. Reducing the content of conductivity anomalies and strengthening the to-be-deposited material is seen to reduce production of such splats or blobs. Other splat limiting steps include smooth finishing of the target surface and low-stress ramp up of the plasma.

摘要翻译： 公开了用于形成具有低缺陷密度的金属化膜的改进的用于铝或类似金属的DC_磁控溅射的靶。 还公开了制造和使用这些靶的方法。 诸如由金属氧化物夹杂物组成的电导率异常可以引起目标表面和等离子体之间的电弧。 电弧会导致过剩的沉积材料以斑块或斑点的形式产生。 减少电导率异常的含量和加强待沉积材料可以减少这种斑块或斑点的产生。 其它限制步骤包括平滑地对目标表面进行精加工和等离子体的低应力升高。

公开(公告)号：US6126791A

公开(公告)日：2000-10-03

申请号：US419827

申请日：1999-10-14

申请人： Vikram Pavate ,  Keith J. Hansen ,  Glen Mori ,  Murali Narasimhan ,  Seshadri Ramaswami ,  Jaim Nulman

发明人： Vikram Pavate ,  Keith J. Hansen ,  Glen Mori ,  Murali Narasimhan ,  Seshadri Ramaswami ,  Jaim Nulman

IPC分类号： C23C14/34 ,  H01L21/285

CPC分类号： C23C14/3414 ,  Y10S29/002 ,  Y10S29/005 ,  Y10T29/49988

摘要： Improved targets for use in DC.sub.-- magnetron sputtering of aluminum or like metals are disclosed for forming metallization films having low defect densities. Methods for manufacturing and using such targets are also disclosed. Conductivity anomalies such as those composed of metal oxide inclusions can induce arcing between the target surface and the plasma. The arcing can lead to production of excessive deposition material in the form of splats or blobs. Reducing the content of conductivity anomalies and strengthening the to-be-deposited material is seen to reduce production of such splats or blobs. Other splat limiting steps include smooth finishing of the target surface and low-stress ramp up of the plasma.

摘要翻译： 公开了用于形成具有低缺陷密度的金属化膜的改进的用于铝或类似金属的直流磁控溅射的靶。 还公开了制造和使用这些靶的方法。 诸如由金属氧化物夹杂物组成的电导率异常可以引起目标表面和等离子体之间的电弧。 电弧会导致过剩的沉积材料以斑块或斑点的形式产生。 减少电导率异常的含量和加强待沉积材料可以减少这种斑块或斑点的产生。 其它限制步骤包括平滑地对目标表面进行精加工和等离子体的低应力升高。

公开(公告)号：US6046100A

公开(公告)日：2000-04-04

申请号：US762868

申请日：1996-12-12

申请人： Seshadri Ramaswami ,  Jaim Nulman

发明人： Seshadri Ramaswami ,  Jaim Nulman

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L21/311

CPC分类号： H01L21/76816

摘要： A method of fabricating an electrically conductive plug on a semiconductor workpiece. A dielectric layer is deposited on the workpiece, and a cavity is etched in the dielectric. An etchant-resistant material is deposited on the wall of the cavity adjacent the cavity mouth so as to form an inwardly-extending lateral protrusion, the etchant-resistant material being resistant to etching by at least one etchant substance which etches said electrically conductive material substantially faster than it etches the etchant resistant material. The cavity is filled by an electrically conductive material. In another aspect of the method, the etchant-resistant material can be omitted. Instead, upper and lower portions of the cavity are etched anisotropically and isotropically, respectively, so as to form a lower portion of the cavity that is wider than the upper portion. In a third aspect of the method, a higher density upper layer of dielectric is deposited over a lower density lower layer of dielectric. The two layers are etched to form a cavity. Because of the upper layer's higher density, it etches more slowly than the lower layer, producing a cavity having an upper portion that is narrower than its lower portion.

摘要翻译： 一种在半导体工件上制造导电插塞的方法。 电介质层沉积在工件上，在电介质中蚀刻空腔。 耐蚀刻材料沉积在邻近空腔口的空腔的壁上，以形成向内延伸的侧向突起，耐蚀刻材料耐蚀刻至少一种腐蚀剂物质，其基本上蚀刻所述导电材料 比蚀刻耐腐蚀材料要快。 空腔由导电材料填充。 在该方法的另一方面，可以省略耐蚀刻材料。 相反，空腔的上部和下部分别被各向异性和各向异性地蚀刻，以便形成比上部更宽的空腔的下部。 在该方法的第三方面，较高密度的电介质上层沉积在较低密度的较低电介质层上。 蚀刻两层以形成空腔。 由于上层的密度较高，所以其蚀刻比下层更缓慢，产生具有比其下部窄的上部的空腔。

公开(公告)号：US5434044A

公开(公告)日：1995-07-18

申请号：US253515

申请日：1994-06-03

申请人： Jaim Nulman ,  Kenny K. Ngan

发明人： Jaim Nulman ,  Kenny K. Ngan

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76876 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915 ,  Y10S438/927 ,  Y10S438/973

摘要： A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.

摘要翻译： 描述了一种在硅表面上形成具有（111）晶体取向表面的氮化钛阻挡层的方法。 该方法包括：在硅表面上沉积第一钛层; 在钛层上溅射氮化钛层; 在溅射的氮化钛层上沉积第二钛层; 然后在含氮气体的存在下退火该结构，并且在不存在含氧气体的情况下，形成具有（111）晶体取向表面和足够厚度的所需氮化钛以提供保护 底层硅对铝的尖峰。 当随后在（111）取向的氮化钛表面上形成铝层时，铝将呈现相同的（111）晶体取向，导致铝层具有增强的电迁移阻力。

公开(公告)号：US5356835A

公开(公告)日：1994-10-18

申请号：US78364

申请日：1993-06-16

申请人： Sasson Somekh ,  Jaim Nulman ,  Mei Chang

发明人： Sasson Somekh ,  Jaim Nulman ,  Mei Chang

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76876 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76877 ,  H01L23/53257 ,  H01L2924/0002 ,  Y10S438/907

摘要： An improved process is described for forming planar tungsten-filled contacts to a silicon substrate in contact openings through an insulating layer which provides for the formation of titanium silicide in and on the silicon surface at the bottom of the contact openings to provide low resistance silicide interconnections between the silicon substrate and the tungsten. A titanium nitride layer is formed over the titanium silicide and on the surfaces of the insulation layer, including the top surface of the insulation layer and the sidewall surfaces of the contact openings through the insulating layer. This titanium nitride layer provides a nucleation layer which permits a good bond to form from the tungsten through the titanium nitride and titanium silicide in the contact openings to the silicon substrate; and from the tungsten through the titanium nitride layer to the insulator material such as silicon dioxide (SO.sub.2), resulting in the formation of low resistance and low defect density contacts.

摘要翻译： 描述了一种改进的方法，用于在通过绝缘层的接触开口中的硅衬底上形成平坦的钨填充触点，其提供了在接触开口底部的硅表面中和硅表面上形成硅化钛以提供低电阻硅化物互连 在硅衬底和钨之间。 在钛硅化物之上和绝缘层的表面上形成氮化钛层，包括绝缘层的顶表面和穿过绝缘层的接触开口的侧壁表面。 该氮化钛层提供成核层，其允许通过氮化钛和硅化钛在与硅衬底的接触开口中从钨形成良好的结合; 并且从钨通过氮化钛层到绝缘体材料如二氧化硅（SO2），导致形成低电阻和低缺陷密度接触。

公开(公告)号：US5250467A

公开(公告)日：1993-10-05

申请号：US677681

申请日：1991-03-29

申请人： Sasson Somekh ,  Jaim Nulman ,  Mei Chang

发明人： Sasson Somekh ,  Jaim Nulman ,  Mei Chang

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76876 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76877 ,  H01L23/53257 ,  H01L2924/0002 ,  Y10S438/907

摘要： An improved process is described for forming planar tungsten-filled contacts to a silicon substrate in contact openings through an insulating layer which provides for the formation of titanium silicide in and on the silicon surface at the bottom of the contact openings to provide low resistance silicide interconnections between the silicon substrate and the tungsten. A titanium nitride layer is formed over the titanium silicide and on the surfaces of the insulation layer, including the top surface of the insulation layer and the sidewall surfaces of the contact openings through the insulating layer. This titanium nitride layer provides a nucleation layer which permits a good bond to form from the tungsten through the titanium nitride and titanium silicide in the contact openings to the silicon substrate; and from the tungsten through the titanium nitride layer to the insulator material such as silicon dioxide (SO.sub.2), resulting in the formation of low resistance and low defect density contacts.

公开(公告)号：US4854727A

公开(公告)日：1989-08-08

申请号：US114542

申请日：1987-10-26

申请人： Michel Pecot ,  Jaim Nulman

发明人： Michel Pecot ,  Jaim Nulman

IPC分类号： G01J5/00 ,  G01J5/04

CPC分类号： G01J5/0003 ,  G01J5/0007 ,  G01J5/041 ,  G01J5/045 ,  G01J5/524 ,  G01J2005/0048 ,  G01J2005/068

摘要： An improved method and apparatus are disclosed for calibrating the emissivity characteristics of a semiconductor wafer within a processing chamber by supporting a sample wafer on a graphite susceptor within the chamber and by comparing the temperature measured within the susceptor in close proximity to the center of the wafer with the temperature measured by the emission of radiation from the surface of the wafer through the walls of the processing chamber. Temperature measurements subsequently made from the radiation emitted from the surface of similar wafers are corrected with reference to the measurement made of the temperature within the susceptor on the sample wafer.

摘要翻译： 公开了一种改进的方法和装置，用于通过将样品晶片支撑在腔室内的石墨感受器上来校准处理室内的半导体晶片的发射率特性，并且通过将基座内测量的温度与晶片的中心相接近 其温度通过从晶片表面通过处理室的壁的辐射而被测量。 随后从相似晶片表面发射的辐射产生的温度测量参照由样品晶片上的基座内的温度进行的测量来校正。