公开(公告)号：US06355522B1

公开(公告)日：2002-03-12

申请号：US09263699

申请日：1999-03-05

申请人： Kent Kuohua Chang ,  John Jianshi Wang ,  Yuesong He

发明人： Kent Kuohua Chang ,  John Jianshi Wang ,  Yuesong He

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide by chemical vapor deposition using a silicon containing gas and a mixture of a phosphorus containing gas and a carrier gas, the first polysilicon layer having a thickness from about 800 Å to about 1,000 Å; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH2Cl2; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 通过使用含硅气体和含磷气体和载气的混合物通过化学气相沉积在隧道氧化物上形成第一多晶硅层，第一多晶硅层具有约800至约的厚度; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括所述第一多晶硅层上的第一氧化物层，所述第一氧化物层上的氮化物层和所述氮化物层上的第二氧化物层; 在所述绝缘层上形成第二多晶硅层; 通过使用WF 6和SiH 2 Cl 2的化学气相沉积在第二多晶硅层上形成硅化钨层; 至少蚀刻第一多晶硅层，第二多晶硅层，绝缘层和硅化钨层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

公开(公告)号：US06281078B1

公开(公告)日：2001-08-28

申请号：US08993344

申请日：1997-12-18

申请人： Kent Kuohua Chang ,  Yuesong He ,  John Jianshi Wang ,  Ken Au

发明人： Kent Kuohua Chang ,  Yuesong He ,  John Jianshi Wang ,  Ken Au

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： Polystringers that cause NAND-type memory core cells to malfunction are covered by ONO fence material. ONO fence is removed so that polystringers may then be removed more readily. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. The device is next exposed to an hydrogen-fluoride solution to remove oxide-based materials, particularly ONO fence. Thereafter, the polystringers are exposed and may thus be removed more readily.

摘要翻译： 导致NAND型存储器核心单元故障的Polystringers被ONO栅栏材料覆盖。 ONO围栏被移除，从而可以更容易地去除多边形。 从NAND型闪速存储器核心单元之间连续地去除SiON层，硅化钨层，第二多晶硅层，ONO电介质和第一多晶硅层，留下ONO栅栏，屏蔽了一些第一多晶硅层材料的去除。 然后将该装置暴露于氟化氢溶液以除去氧化物基材料，特别是ONO栅栏。 此后，暴露多股线，因此可以更容易地被去除。

公开(公告)号：US6063668A

公开(公告)日：2000-05-16

申请号：US993446

申请日：1997-12-18

申请人： Yuesong He ,  Kent Kuohua Chang ,  John Jianshi Wang

发明人： Yuesong He ,  Kent Kuohua Chang ,  John Jianshi Wang

IPC分类号： H01L21/311 ,  H01L21/8247

CPC分类号： H01L27/11517 ,  H01L21/31116

摘要： A layer of polysilicon is deposited over an oxide layer on top of a silicon substrate, with core field oxide and active regions, and patterned. An oxide mask is then added. Next, the oxide mask and the layer of polysilicon are removed from above the core field oxide regions. Next, a second layer of polysilicon is deposited and etched to form polysilicon spacers. Later, an ONO dielectric, a third polysilicon layer, a tungsten silicide layer, and SiON layers are successively formed and patterned. The polysilicon spacers effectively seal any recesses that may occur in the edges of the first polysilicon layer to prevent harboring of subsequently added polysilicon material. Accordingly, NAND-type flash memory core cells cannot be electrically shorted by polysilicon material, so called "polystringers", present in such recesses.

摘要翻译： 在硅衬底顶部的氧化物层上沉积多晶硅层，其中具有核心场氧化物和有源区域并且被图案化。 然后加入氧化物掩模。 接下来，从核心场氧化物区域的上方去除氧化物掩模和多晶硅层。 接下来，沉积和蚀刻第二层多晶硅以形成多晶硅间隔物。 随后，依次形成和图案化ONO电介质，第三多晶硅层，硅化钨层和SiON层。 多晶硅间隔物有效地密封可能在第一多晶硅层的边缘中发生的任何凹陷，以防止随后添加的多晶硅材料。 因此，NAND型闪速存储器核心单元不能被存在于这种凹槽中的多晶硅材料（即所谓的“超弦波”）电短路。

公开(公告)号：US06177312B1

公开(公告)日：2001-01-23

申请号：US09048459

申请日：1998-03-26

申请人： Yuesong He ,  John Jianshi Wang ,  Toru Ishigaki ,  Kent Kuohua Chang ,  Effiong Ibok

发明人： Yuesong He ,  John Jianshi Wang ,  Toru Ishigaki ,  Kent Kuohua Chang ,  Effiong Ibok

IPC分类号： H01L2128

CPC分类号： H01L21/28211 ,  H01L21/31116 ,  H01L21/3185 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11536 ,  Y10S438/974

摘要： This invention relates to a method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of said device, wherein at least some of the contaminate nitrogen has formed a bond with the surface of the silicon substrate in contact with the gate oxide layer in said gate region, said method comprising: contacting said gate oxide layer and contaminate nitrogen with a gas comprising ozone at a temperature of about 850° C. to about 950° C. for an effective period of time to break said bond; and removing said gate oxide layer and contaminate nitrogen from said surface of said silicon substrate.

摘要翻译： 本发明涉及一种在制造所述装置期间从非易失性存储装置的外围栅极区域去除污染氮的方法，其中至少一些污染氮已经与硅衬底的表面形成了接触， 所述栅极区域中的栅极氧化物层，所述方法包括：使接触所述栅极氧化物层并且在约850℃至约950℃的温度下将含有包含臭氧的气体氮气与有毒时间隔离以破坏所述 键; 以及去除所述栅极氧化物层并从所述硅衬底的所述表面污染氮。

公开(公告)号：US6066873A

公开(公告)日：2000-05-23

申请号：US271330

申请日：1999-03-18

申请人： John J. Wang ,  Yuesong He ,  Kent Kuohua Chang

发明人： John J. Wang ,  Yuesong He ,  Kent Kuohua Chang

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/8239 ,  H01L39/78

CPC分类号： H01L28/40 ,  H01L27/1052 ,  H01L21/3143 ,  Y10S438/97

摘要： A method and apparatus for an integrated circuit on a semiconductor substrate having good metal contact points. A first polysilicon layer is formed onto the substrate, and is etched to provide contact regions to the substrate. An ONO layer is formed onto the first polysilicon layer. A second polysilicon layer is formed onto the ONO layer, and a metal silicide layer is formed onto the second polysilicon layer. The second polysilicon layer and the metal silicide layer are etched at particular locations in order to form contact regions to the first polysilicon layer and to the substrate. A selective layer is formed onto the second polysilicon layer, the selective layer being etch selective with respect to the first polysilicon layer. An interlayer dielectric is formed onto the selective layer. A first etching is performed to provide a contact path through the interlayer dielectric, and then a second etching is performed to provide a contact path through the selective layer. Based on these two contact paths, a contact point can be provided externally to the first polysilicon layer.

摘要翻译： 一种具有良好金属接触点的半导体衬底上集成电路的方法和装置。 第一多晶硅层形成在衬底上，并被蚀刻以提供与衬底的接触区域。 在第一多晶硅层上形成ONO层。 在ONO层上形成第二多晶硅层，在第二多晶硅层上形成金属硅化物层。 在特定位置蚀刻第二多晶硅层和金属硅化物层，以便形成与第一多晶硅层和衬底的接触区域。 选择层形成在第二多晶硅层上，选择层相对于第一多晶硅层具有蚀刻选择性。 在选择层上形成层间电介质。 执行第一蚀刻以提供通过层间电介质的接触路径，然后执行第二蚀刻以提供穿过选择层的接触路径。 基于这两个接触路径，可以在第一多晶硅层的外部设置接触点。

公开(公告)号：US06204159B1

公开(公告)日：2001-03-20

申请号：US09349603

申请日：1999-07-09

申请人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  Yuesong He

发明人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  Yuesong He

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11546

摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a core region and a periphery region, the core region including a flash memory cell area and a select gate area and the periphery region including a high voltage transistor area and low voltage transistor area; depositing a first doped amorphous silicon layer over at least a portion of the first oxide layer; depositing a dielectric layer over at least a portion of the first doped amorphous silicon layer; removing portions of the first oxide layer, the first doped amorphous silicon layer, and the dielectric layer in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; growing a second oxide layer over at least a portion of the substrate in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; removing portions of the second oxide layer in the select gate area of the core region and the low voltage transistor area the periphery region; growing a third oxide layer over at least a portion of the substrate in the select gate area of the core region and the low voltage transistor area of the periphery region; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer, the second oxide layer and the third oxide layer; and forming a flash memory cell in the flash memory cell area of the core region, a select gate transistor in the select gate area of the core region, a low voltage transistor in the low voltage transistor area of the periphery region, and a high voltage transistor in the high voltage transistor area of the periphery region.

摘要翻译： 在一个实施例中，本发明涉及一种形成NAND型快闪存储器件的方法，包括以下步骤：在衬底的至少一部分上生长第一氧化层，所述衬底包括芯区域和周边区域， 芯区域包括闪存单元区域和选择栅极区域，并且包括高压晶体管区域和低压晶体管区域的周边区域; 在所述第一氧化物层的至少一部分上沉积第一掺杂非晶硅层; 在所述第一掺杂非晶硅层的至少一部分上沉积介电层; 去除所述芯区域的所述选择栅极区域中的所述第一氧化物层，所述第一掺杂非晶硅层和所述介电层的部分，以及所述高压晶体管区域和所述低电压晶体管区域的外围区域; 在所述芯区域的所述选择栅极区域中的所述衬底的至少一部分和所述高压晶体管区域和所述低电压晶体管区域的外围区域上生长第二氧化物层; 去除芯区域的选择栅极区域中的第二氧化物层的部分和外围区域的低电压晶体管区域; 在芯区域的选择栅极区域和外围区域的低电压晶体管区域的至少一部分衬底上生长第三氧化物层; 在所述电介质层，所述第二氧化物层和所述第三氧化物层的至少一部分上沉积第二掺杂非晶硅层; 以及在芯区的闪速存储单元区域中形成闪速存储单元，在芯区的选择栅极区中的选择栅极晶体管，外围区的低电压晶体管区中的低电压晶体管，以及高电压 晶体管在周边区域的高压晶体管区域。

公开(公告)号：US6146795A

公开(公告)日：2000-11-14

申请号：US146032

申请日：1998-09-02

申请人： Jiahua Huang ,  Yuesong He ,  Kent Kuohua Chang

发明人： Jiahua Huang ,  Yuesong He ,  Kent Kuohua Chang

IPC分类号： G03F7/36 ,  G03F7/40

CPC分类号： G03F7/40 ,  G03F7/36

摘要： Tunnel oxide degradation is reduced by reducing residual photoresist material in open areas of a mask pattern. Embodiments include detecting residual photoresist in an exposed underlying region of a substrate by x-ray spectroscopy and descumming in response to detected residual photoresist.

摘要翻译： 通过在掩模图案的开放区域中减少残留光致抗蚀剂材料来减少隧道氧化物降解。 实施例包括通过X射线光谱检测在基底的暴露下面的区域中的残留光致抗蚀剂，并响应于检测到的残留光致抗蚀剂除去。

公开(公告)号：US6114230A

公开(公告)日：2000-09-05

申请号：US993443

申请日：1997-12-18

申请人： Kent Kuohua Chang ,  Yuesong He ,  David Chi

发明人： Kent Kuohua Chang ,  Yuesong He ,  David Chi

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/511

摘要： A polysilicon-based floating gate is formed so as to be resistant to oxidation that occurs during multiple thermo-cycles in fabrication. Accordingly, edge erase times in NOR-type memory devices may be minimized. Additionally, manufacture of oxidation resistant floating gates reduces variations in edge erase times among multiple NOR-type memory devices. A layer of amorphous silicon is deposited over a silicon substrate by directing a mixture of silane and a phosphene-helium gas mixture at the surface of the silicon substrate. Later, N+ ions are implanted into the amorphous silicon. The amorphous silicon layer is then etched so as to overlap slightly with regions that will later correspond to the source and drain regions. Next, a lower oxide layer of an ONO dielectric is deposited and the device is heated. A thermo-cycle is eliminated by heating the amorphous silicon during formation of the oxide layer rather than immediately following its deposition. Later, the nitride and oxide layers of the ONO dielectric, a second polysilicon layer, a tungsten silicide layer, and SiON layers are successively formed.

摘要翻译： 形成基于多晶硅的浮栅，以便在制造中的多个热循环期间耐氧化。 因此，NOR型存储器件中的边沿擦除时间可以最小化。 此外，抗氧化浮动栅极的制造减少了多个NOR型存储器件之间的边缘擦除时间的变化。 通过在硅衬底的表面处引导硅烷和磷 - 氦气混合物的混合物，在硅衬底上沉积非晶硅层。 之后，将N +离子注入到非晶硅中。 然后蚀刻非晶硅层，以便稍后与稍后对应于源极和漏极区的区域重叠。 接下来，沉积ONO电介质的低氧化物层，并加热该器件。 通过在形成氧化物层期间加热非晶硅而不是在其沉积之后立即消除热循环。 随后，依次形成ONO电介质，第二多晶硅层，硅化钨层和SiON层的氮化物层和氧化物层。

公开(公告)号：US06184084B2

公开(公告)日：2001-02-06

申请号：US09263701

申请日：1999-03-05

申请人： David Chi ,  Kent Kuohua Chang ,  Yuesong He

发明人： David Chi ,  Kent Kuohua Chang ,  Yuesong He

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/3212

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer; forming a second polysilicon layer over the insulating layer by depositing an second polysilicon layer having a first thickness, and then using chemical mechanical polishing to form a second polysilicon layer having a second thickness, wherein the second thickness is at least about 25% less than the first thickness; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH4; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层; 通过沉积具有第一厚度的第二多晶硅层，然后使用化学机械抛光形成具有第二厚度的第二多晶硅层，在所述绝缘层上形成第二多晶硅层，其中所述第二厚度比所述第二厚度小至少约25％ 第一厚度 通过使用WF6和SiH4的化学气相沉积在第二多晶硅层上形成硅化钨层; 至少蚀刻第一多晶硅层，第二多晶硅层，绝缘层和硅化钨层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

公开(公告)号：US5981339A

公开(公告)日：1999-11-09

申请号：US45013

申请日：1998-03-20

申请人： Kent Kuohua Chang ,  David Chi ,  Yuesong He

发明人： Kent Kuohua Chang ,  David Chi ,  Yuesong He

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8247

CPC分类号： H01L21/28202 ,  H01L21/28211 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell involving the steps of: forming a tunnel oxide on a substrate; forming an in situ phosphorus doped polysilicon layer over the tunnel oxide by low pressure chemical vapor deposition at a temperature between about 610.degree. C. and about 630.degree. C., wherein the in situ phosphorus doped polysilicon layer comprises from about 1.times.10.sup.19 atoms/cm.sup.3 to about 5.times.10.sup.19 atoms/cm.sup.3 of phosphorus; forming an insulating layer over the in situ phosphorus doped polysilicon layer; forming a conductive layer over the insulating layer; etching the in situ phosphorus doped polysilicon layer, the conductive layer and the insulating layer, thereby defining one or more stacked gate structures; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are self-aligned by the stacked gate structures, thereby forming one or more memory cells.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪存单元的方法，该方法包括以下步骤：在衬底上形成隧道氧化物; 在约610℃至约630℃的温度下通过低压化学气相沉积在隧道氧化物上形成原位磷掺杂多晶硅层，其中原位磷掺杂多晶硅层包含约1×1019原子/ cm3至 约5×1019原子/ cm3磷; 在原位磷掺杂多晶硅层上形成绝缘层; 在所述绝缘层上形成导电层; 蚀刻原位磷掺杂多晶硅层，导电层和绝缘层，从而限定一个或多个堆叠栅极结构; 以及在所述衬底中形成源区和漏区，其中所述源极区和所述漏区由所述堆叠栅极结构自对准，从而形成一个或多个存储单元。