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    CMOS back-gated keeper technique
    1.
    发明授权
    CMOS back-gated keeper technique 失效

    公开(公告)号：US07750682B2

    公开(公告)日：2010-07-06

    申请号：US12045500

    申请日：2008-03-10

    申请人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

    发明人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

    IPC分类号： H03K19/094

    CPC分类号： H03K19/0008 ,  H03K3/356104 ,  H03K2217/0018

    摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

    CMOS back-gated keeper technique
    2.
    发明授权
    CMOS back-gated keeper technique 失效
    CMOS后门控技术

    公开(公告)号：US07750677B2

    公开(公告)日：2010-07-06

    申请号：US12538652

    申请日：2009-08-10

    申请人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

    发明人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

    IPC分类号： H03K19/21

    CPC分类号： H03K19/0008 ,  H03K3/356104 ,  H03K2217/0018

    摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

    摘要翻译： 详细描述了利用并接触MOSFET器件的第四端子（衬底/本体）的逻辑电路和栅极的构造和操作的新颖方法。 新颖的结构和操作提供了当主动接通（以增加过驱动和性能）时以及在关闭时较高的相对阈值电压（以减少泄漏功率）时将这种体接触的MOSFET器件保持在较低的阈值电压（VTh）。 因为门的门限电位与其电位相反地移动，所以一般来说，给定器件的器件必须与器件的漏极电压相反，以达到改善器件所需的阈值电位调制效应 ，电路，门和逻辑家庭操作。

    CMOS BACK-GATED KEEPER TECHNIQUE
    3.
    发明申请
    CMOS BACK-GATED KEEPER TECHNIQUE 失效

    公开(公告)号：US20090295432A1

    公开(公告)日：2009-12-03

    申请号：US12538652

    申请日：2009-08-10

    申请人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

    发明人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

    IPC分类号： H03K19/20

    CPC分类号： H03K19/0008 ,  H03K3/356104 ,  H03K2217/0018

    摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

    摘要翻译： 详细描述了利用并接触MOSFET器件的第四端子（衬底/本体）的逻辑电路和栅极的构造和操作的新颖方法。 新颖的结构和操作提供了当主动接通（以增加过驱动和性能）时以及在关闭时较高的相对阈值电压（以减少泄漏功率）时将这种体接触的MOSFET器件保持在较低的阈值电压（VTh）。 因为门的门限电位与其电位相反地移动，所以一般来说，给定器件的器件必须与器件的漏极电压相反，以达到改善器件所需的阈值电位调制效应 ，电路，门和逻辑家庭操作。

    CMOS BACK-GATED KEEPER TECHNIQUE
    4.
    发明申请
    CMOS BACK-GATED KEEPER TECHNIQUE 失效

    公开(公告)号：US20090224803A1

    公开(公告)日：2009-09-10

    申请号：US12045500

    申请日：2008-03-10

    申请人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

    发明人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

    IPC分类号： H03K19/20

    CPC分类号： H03K19/0008 ,  H03K3/356104 ,  H03K2217/0018

    摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

    Method for fabricating finFET with merged fins and vertical silicide
    6.
    发明授权
    Method for fabricating finFET with merged fins and vertical silicide 有权
    使用合并翅片和垂直硅化物制造finFET的方法

    公开(公告)号：US08455313B1

    公开(公告)日：2013-06-04

    申请号：US13617709

    申请日：2012-09-14

    申请人： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

    发明人： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

    IPC分类号： H01L21/336

    CPC分类号： H01L29/41791 ,  H01L29/66795

    摘要： A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.

    摘要翻译： 提供了一种用于制造finFET器件的方法。 翅片结构形成在BOX层上。 翅片结构包括半导体层并沿第一方向延伸。 栅极叠层形成在鳍状结构上的BOX层上并沿第二方向延伸。 栅极堆叠包括高K电介质层和金属栅极。 栅极间隔物形成在栅极堆叠的侧壁上，并且沉积外延层以使翅片结构合并。 植入离子以形成源极和漏极区，并且在栅极间隔物的侧壁上形成虚设间隔物。 虚拟间隔物用作掩模以凹进或完全去除外延层的暴露部分。 硅化形成邻接源极和漏极区域的硅化物区域，并且每个都包括位于源极或漏极区域的垂直侧壁上的垂直部分。

    finFET with merged fins and vertical silicide
    7.
    发明授权
    finFET with merged fins and vertical silicide 有权
    finFET具有合并翅片和垂直硅化物

    公开(公告)号：US08637931B2

    公开(公告)日：2014-01-28

    申请号：US13337874

    申请日：2011-12-27

    申请人： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

    发明人： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

    IPC分类号： H01L27/12

    CPC分类号： H01L29/41791 ,  H01L29/66795

    摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.

    摘要翻译： 提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于 翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。 翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。 栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。 硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

    FINFET WITH MERGED FINS AND VERTICAL SILICIDE
    8.
    发明申请
    FINFET WITH MERGED FINS AND VERTICAL SILICIDE 有权
    具有合并的FINS和垂直硅胶的FINFET

    公开(公告)号：US20130161744A1

    公开(公告)日：2013-06-27

    申请号：US13337874

    申请日：2011-12-27

    申请人： Veeraraghavan S. BASKER ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

    发明人： Veeraraghavan S. BASKER ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

    IPC分类号： H01L27/12 ,  H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/41791 ,  H01L29/66795

    摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.

    摘要翻译： 提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于 翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。 翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。 栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。 硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

    Domino logic circuit having multiplicity of gate dielectric thicknesses
    9.
    发明授权
    Domino logic circuit having multiplicity of gate dielectric thicknesses 有权
    具有多个栅介质厚度的多米诺逻辑电路

    公开(公告)号：US06404236B1

    公开(公告)日：2002-06-11

    申请号：US09811967

    申请日：2001-03-19

    申请人： Kerry Bernstein ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Edward Joseph Nowak ,  Minh Ho Tong

    发明人： Kerry Bernstein ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Edward Joseph Nowak ,  Minh Ho Tong

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. Connected to a power supply, the precharge transistor receives a clock input. The isolation transistor is connected to ground and also receives the clock input. Each of the input transistors, which are coupled between the precharge transistor and the isolation transistor, receives a signal input. The gate dielectric thickness of the evaluate transistors is less than the gate dielectric thickness of the precharge transistor.

    摘要翻译： 公开了具有时钟预充电的多米诺骨牌逻辑电路。 多米诺骨牌逻辑电路包括预充电晶体管，隔离晶体管和多个评估晶体管。 连接到电源，预充电晶体管接收时钟输入。 隔离晶体管连接到地，并接收时钟输入。 耦合在预充电晶体管和隔离晶体管之间的每个输入晶体管接收信号输入。 评估晶体管的栅介质厚度小于预充电晶体管的栅介质厚度。