利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.024 秒)

    Transceiver with latency alignment circuitry
    1.
    发明授权
    Transceiver with latency alignment circuitry 有权
    具有延迟对准电路的收发器

    公开(公告)号：US06643752B1

    公开(公告)日：2003-11-04

    申请号：US09458582

    申请日：1999-12-09

    申请人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John B. Dillon

    发明人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John B. Dillon

    IPC分类号： G06F1200

    CPC分类号： G06F13/405 ,  G06F13/4022 ,  G06F13/4243

    摘要： A transceiver system is described. A secondary memory module is coupled to a primary channel for receiving data and signals from a controller. The secondary memory module comprises a memory and a secondary channel for transmitting the data and control signals to the memory. The secondary memory module further comprises a transceiver coupled to the primary channel and the secondary channel. The transceiver is designed to electrically isolate the secondary channel from the primary channel. The transceiver is a low latency repeater to permit the data and the control signals from the controller to reach the memory, such that a latency of a data request from the controller is independent of a distance of the transceiver from the controller.

    摘要翻译： 描述收发器系统。 次存储器模块耦合到主信道，用于从控制器接收数据和信号。 辅助存储器模块包括用于将数据和控制信号发送到存储器的存储器和辅助通道。 次存储器模块还包括耦合到主信道和次信道的收发器。 收发器被设计为将次级通道与主通道电隔离。 收发器是一个低延迟中继器，允许来自控制器的数据和控制信号到达存储器，使得来自控制器的数据请求的等待时间与收发器与控制器的距离无关。

    Transceiver with latency alignment circuitry
    2.
    发明授权
    Transceiver with latency alignment circuitry 有权
    具有延迟对准电路的收发器

    公开(公告)号：US08086812B2

    公开(公告)日：2011-12-27

    申请号：US11465230

    申请日：2006-08-17

    申请人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John B. Dillon ,  Nancy D. Dillon, legal representative

    发明人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John B. Dillon

    IPC分类号： G06F12/00

    CPC分类号： G06F13/405 ,  G06F13/4022 ,  G06F13/4243

    摘要： In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

    摘要翻译： 在收发机系统中，第一接口使用第一时钟信号从第一信道接收数据，并使用第二时钟信号将数据发送到第一信道。 第二接口使用第三时钟信号从第二信道接收数据，并使用第四时钟信号将数据发送到第二信道。 重新定时器使用第一时钟信号从第一信道接收数据，并使用第四时钟信号将数据重传到第二信道。

    Transceiver with latency alignment circuitry
    3.
    发明申请
    Transceiver with latency alignment circuitry 有权
    具有延迟对准电路的收发器

    公开(公告)号：US20050160247A1

    公开(公告)日：2005-07-21

    申请号：US11078577

    申请日：2005-03-11

    申请人： John Dillon ,  Nancy Dillon ,  Kevin Donnelly ,  Mark Johnson ,  Chanh Tran

    发明人： John Dillon ,  Nancy Dillon ,  Kevin Donnelly ,  Mark Johnson ,  Chanh Tran

    IPC分类号： G06F13/40 ,  G06F13/00

    CPC分类号： G06F13/405 ,  G06F13/4022 ,  G06F13/4243

    摘要： A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register stores a control parameter that specifies a drive strength adjustment to the signals to transmit over the plurality of conductors to the memory device using the transmitter.

    摘要翻译： 收发器设备包括发射器，用于将信号通过多个导体传输到存储器件。 接口从耦合到控制器设备的串行通信路径接收控制信息。 控制信息作为使用发射机的信号提供给存储装置。 寄存器存储控制参数，该控制参数指定使用发射机将多个导体发送到存储器件的信号的驱动强度调整。

    TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY
    5.
    发明申请
    TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY 有权
    具有延迟对准电路的收发器

    公开(公告)号：US20070011426A1

    公开(公告)日：2007-01-11

    申请号：US11465230

    申请日：2006-08-17

    申请人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John Dillon ,  Nancy Dillon

    发明人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John Dillon ,  Nancy Dillon

    IPC分类号： G06F13/00

    CPC分类号： G06F13/405 ,  G06F13/4022 ,  G06F13/4243

    摘要： In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

    摘要翻译： 在收发机系统中，第一接口使用第一时钟信号从第一信道接收数据，并使用第二时钟信号将数据发送到第一信道。 第二接口使用第三时钟信号从第二信道接收数据，并使用第四时钟信号将数据发送到第二信道。 重新定时器使用第一时钟信号从第一信道接收数据，并使用第四时钟信号将数据重传到第二信道。

    Transceiver with latency alignment circuitry
    6.
    发明授权
    Transceiver with latency alignment circuitry 有权
    具有延迟对准电路的收发器

    公开(公告)号：US08458426B2

    公开(公告)日：2013-06-04

    申请号：US11624966

    申请日：2007-01-19

    申请人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  Nancy D. Dillon

    发明人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John B. Dillon

    IPC分类号： G06F12/00

    CPC分类号： G06F13/405 ,  G06F13/4022 ,  G06F13/4243

    摘要： In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

    摘要翻译： 在收发机系统中，第一接口使用第一时钟信号从第一信道接收数据，并使用第二时钟信号将数据发送到第一信道。 第二接口使用第三时钟信号从第二信道接收数据，并使用第四时钟信号将数据发送到第二信道。 重新定时器使用第一时钟信号从第一信道接收数据，并使用第四时钟信号将数据重传到第二信道。

    Transceiver with latency alignment circuitry
    8.
    发明申请
    Transceiver with latency alignment circuitry 有权
    具有延迟对准电路的收发器

    公开(公告)号：US20050149685A1

    公开(公告)日：2005-07-07

    申请号：US11058333

    申请日：2005-02-15

    申请人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John Dillon ,  Nancy Dillon

    发明人： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John Dillon ,  Nancy Dillon

    IPC分类号： G06F13/40 ,  G06F13/00

    CPC分类号： G06F13/405 ,  G06F13/4022 ,  G06F13/4243

    摘要： A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the master device. The plurality of values includes a first value that specifies a transmit timing adjustment to the second signal to transmit to the master device by the transmitter.

    摘要翻译： 收发机包括第一接口，用于通过第一信道从存储器装置接收第一信号。 发射机通过第二信道将表示第一信号的第二信号发送到主设备。 多个寄存器存储由主设备提供的多个值。 多个值包括第一值，该第一值指定由发送器向主设备发送的第二信号的发送定时调整。

    Interface test circuit
    9.
    发明申请
    Interface test circuit 失效
    接口测试电路

    公开(公告)号：US20070257693A1

    公开(公告)日：2007-11-08

    申请号：US11417964

    申请日：2006-05-03

    申请人： Bret Stott ,  Philip Yeung ,  John Brooks ,  Benedict Lau ,  Chanh Tran ,  Eugene Ho

    发明人： Bret Stott ,  Philip Yeung ,  John Brooks ,  Benedict Lau ,  Chanh Tran ,  Eugene Ho

    IPC分类号： G01R31/02

    CPC分类号： G01R31/31716 ,  G11C29/022

    摘要： An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

    摘要翻译： 描述了集成电路。 集成电路包括包括发射机和接收机的接口电路。 集成电路中的发生器选择性地耦合到发射机。 发生器将提供在测试操作模式期间由发射器输出的测试序列。 集成电路中的存储器选择性地耦合到发生器和接收器。 存储器是接收并同步测试序列和对应于由接收机接收的测试序列的信号。 集成电路中的逻辑电路是比较测试序列和信号。

    ADAPTIVE IMPEDANCE OUTPUT DRIVER CIRCUIT
    10.
    发明申请
    ADAPTIVE IMPEDANCE OUTPUT DRIVER CIRCUIT 有权
    自适应阻抗输出驱动电路

    公开(公告)号：US20050057275A1

    公开(公告)日：2005-03-17

    申请号：US10662204

    申请日：2003-09-12

    申请人： Huy Ngyuen ,  Chanh Tran

    发明人： Huy Ngyuen ,  Chanh Tran

    IPC分类号： H03K19/00 ,  H03K19/003

    CPC分类号： H03K19/00384 ,  H03K19/0005

    摘要： Disclosed is an output driver having an output port for outputting a data signal, a level shifter for driving a current to the output port in response to a current control input, an adjustable impedance controller for generating an impedance adjustment signal; an output impedance compensator for adjusting the impedance of the level shifter in accordance with the impedance adjustment signal and in accordance with a reference voltage, and a tracking circuit, including a process and temperature monitor responsive to manufacturing process and temperature variations of the output driver, a frequency monitor responsive to the frequency of an input clock signal, and a voltage supply monitor responsive to an internal power supply voltage. The process and temperature monitor, frequency monitor and voltage supply monitor are interconnected so as to generate the reference voltage.

    摘要翻译： 公开了一种输出驱动器，具有用于输出数据信号的输出端口，用于响应于电流控制输入将电流驱动到输出端口的电平移位器，用于产生阻抗调整信号的可调阻抗控制器; 输出阻抗补偿器，用于根据阻抗调整信号并根据参考电压调整电平移位器的阻抗;以及跟踪电路，包括响应于制造过程和输出驱动器的温度变化的过程和温度监视器， 响应于输入时钟信号的频率的频率监视器和响应于内部电源电压的电压供应监视器。 过程和温度监视器，频率监视器和电压监视器互连，以产生参考电压。