公开(公告)号：US5598364A

公开(公告)日：1997-01-28

申请号：US560002

申请日：1995-11-17

申请人： Kevin J. McCall ,  Janos Kovacs ,  Wyn Palmer

发明人： Kevin J. McCall ,  Janos Kovacs ,  Wyn Palmer

IPC分类号： G11B20/10 ,  G11B20/22 ,  H03K5/135 ,  H03L7/099 ,  G11C13/00

CPC分类号： H03L7/0805 ,  G11B20/10 ,  H03K5/135 ,  H03L7/0995

摘要： A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

摘要翻译： 写入预补偿电路包括多个电流控制延迟缓冲器，连接形成具有可选输出抽头的延迟线。 每个延迟缓冲器的精确延迟可以通过从主控制电流导出的次级控制电流来控制，使得精确的延迟是振荡器周期的精确百分比。 主控制电流也用于控制由延迟缓冲器的电流控制环形振荡器产生的主写时钟的周期。 写预补偿方法包括以下步骤：控制用于在电流控制延迟线中产生主写时钟和延迟缓冲器中的电流的电流控制环形振荡器中的延迟缓冲器中的电流，以通过振荡器的延迟缓冲器和延迟来维持延迟 以预定比例相互排列。

公开(公告)号：US6147531A

公开(公告)日：2000-11-14

申请号：US112889

申请日：1998-07-09

申请人： Kevin J. McCall ,  Janos Kovacs

发明人： Kevin J. McCall ,  Janos Kovacs

IPC分类号： G11B20/10 ,  H03L7/081 ,  H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0891 ,  G11B20/10009 ,  H03L7/0812

摘要： A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.

摘要翻译： 用于将数据信号写入驱动器的读/写盘驱动系统中的写通道包括一可变延迟电路，其具有多个用于校正非线性转换移位的可选抽头; 以及响应于用于控制可变电路的延迟的数据信号的延迟锁定环电路。

公开(公告)号：US6144981A

公开(公告)日：2000-11-07

申请号：US174944

申请日：1998-10-19

申请人： Janos Kovacs ,  Kevin J. McCall

发明人： Janos Kovacs ,  Kevin J. McCall

IPC分类号： H03H11/04 ,  G06G7/02

CPC分类号： H03H11/0444

摘要： A programmable pulse slimmer system for a low pass ladder filter includes a filter input current source for providing to a low pass ladder filter the input signal to be filtered; and a high frequency boost current source for injecting into the low pass ladder filter forward of the first inductor device a high frequency load current which is a scaled inverse replica of the input signal to provide gain at the high frequency end of the low pass band of the low pass ladder filter.

摘要翻译： 用于低通梯形滤波器的可编程脉冲微型系统包括滤波器输入电流源，用于向低通梯形滤波器提供要滤波的输入信号; 以及高频升压电流源，用于向第一电感器件前面的低通梯形滤波器注入高频负载电流，该高频负载电流是输入信号的缩放反向复制品，以在低通带的高频端提供增益 低通梯过滤器。

公开(公告)号：US5541532A

公开(公告)日：1996-07-30

申请号：US516384

申请日：1995-08-17

申请人： Kevin J. McCall

发明人： Kevin J. McCall

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/018528 ,  H03K19/00384

摘要： An all MOS single-ended to differential level converter including: first and second source follower circuits each including first and second PMOS semiconductors each having a drain, a source and a gate electrode; a current source commonly connected to the drain electrodes of the first and second PMOS semiconductors; an input circuit for providing to one of the gate electrodes a single-ended input signal and to the other an inverted single-ended input signal; and first and second load impedances connected to the source electrodes of the first and second PMOS semiconductors, respectively, for providing output analog differential signals at a level which is a function of the load impedances and current source magnitude.

摘要翻译： 所有MOS单端到差分电平转换器包括：第一和第二源极跟随器电路，每个包括第一和第二PMOS半导体，每个具有漏极，源极和栅极电极; 通常连接到第一和第二PMOS半导体的漏电极的电流源; 输入电路，用于向一个栅电极提供单端输入信号，另一个提供反相的单端输入信号; 以及分别连接到第一和第二PMOS半导体的源电极的第一和第二负载阻抗，用于以作为负载阻抗和电流源大小的函数的电平提供输出模拟差分信号。

公开(公告)号：US06748038B1

公开(公告)日：2004-06-08

申请号：US09415545

申请日：1999-10-08

申请人： Kevin J. McCall

发明人： Kevin J. McCall

IPC分类号： H04L2708

CPC分类号： H03M1/185

摘要： A method is provided for determining the actual amplitude of a signal relative to a predetermined amplitude. According to the method, two samples of the signal are squared to produce two squared samples, and the sum of the two squared samples minus the square of the predetermined amplitude is calculated to produce a difference of squares. A shift operation is performed on the difference of squares to determine a difference between the actual amplitude and the predetermined amplitude. In a preferred embodiment, two consecutive samples of the signal are taken at four times the frequency of the signal. Also provided is a circuit device that includes an A/D converter, a variable gain amplifier, and a feedback loop. The A/D converter converts an analog signal into a digital signal, and the variable gain amplifier adjusts the amplitude of the analog signal. The feedback loop controls the variable gain amplifier based on a difference between the amplitude of the analog signal and a predetermined amplitude. Further, the feedback loop calculates the difference by squaring two samples of the digital signal, summing the two squared samples and subtracting the square of the predetermined amplitude to produce a result, and shifting the result.

摘要翻译： 提供了一种用于确定信号相对于预定幅度的实际振幅的方法。 根据该方法，将两个信号样本平方以产生两个平方样本，并且计算两个平方样本的和减去预定幅度的平方，得到平方差。 对平方差执行移位操作，以确定实际振幅和预定振幅之间的差。 在优选实施例中，信号的两个连续采样是信号频率的四倍。 还提供了包括A / D转换器，可变增益放大器和反馈回路的电路装置。 A / D转换器将模拟信号转换为数字信号，可变增益放大器调整模拟信号的幅度。 反馈回路基于模拟信号的幅度与预定幅度之差来控制可变增益放大器。 此外，反馈环路通过对数字信号的两个采样进行平方来计算差值，对两个平方采样求和并减去预定幅度的平方以产生结果，并移位结果。

公开(公告)号：US06172569B2

公开(公告)日：2001-01-09

申请号：US09270399

申请日：1999-03-16

申请人： Kevin J. McCall ,  George R. Spaulding, Jr.

发明人： Kevin J. McCall ,  George R. Spaulding, Jr.

IPC分类号： H03F3191

CPC分类号： H03H11/0422 ,  H03H11/54 ,  H03J3/04

摘要： A transconductance filter control system for compensating for drift in transconductance of a slave transconductance amplifier in a continuous time transconductance filter including: a master transconductance amplifier having an output which is a function of its transconductance and a control input for controlling the transconductance of the master transconductance amplifier; a tuning signal source for providing a tuning signal representative of a preselected characteristic of the transconductance filter; a comparing circuit, responsive to any deviation from a predetermined difference between the tuning signal and the output of the master transconductance amplifier, representative of a deviation of the transconductance of the master transconductance amplifier, for providing a compensation signal; and a circuit for applying the compensation signal to the control input of the master transconductance amplifier and to the control input of the slave transconductance amplifier in the transconductance filter to adjust the transconductance of both the master and slave transconductance amplifiers and restore the predetermined difference between the tuning signal and the output of the master transconductance amplifier.

摘要翻译： 一种用于补偿连续时间跨导滤波器中从跨导放大器的跨导漂移的跨导滤波器控制系统，包括：具有作为其跨导的函数的输出的主跨导放大器和用于控制主跨导的跨导的控制输入 放大器 调谐信号源，用于提供表示跨导滤波器的预选特性的调谐信号; 比较电路，响应于调谐信号和主跨导放大器的输出之间的预定差异的任何偏差，代表主跨导放大器的跨导的偏差，用于提供补偿信号; 以及用于将补偿信号施加到主跨导放大器的控制输入端和跨导滤波器中的从跨导放大器的控制输入的电路，以调整主跨导放大器和从器件跨导放大器的跨导，并恢复 调谐信号和主跨导放大器的输出。

公开(公告)号：US5262685A

公开(公告)日：1993-11-16

申请号：US778350

申请日：1991-10-16

申请人： Michael J. Demler ,  Kevin J. McCall

发明人： Michael J. Demler ,  Kevin J. McCall

IPC分类号： G11C27/02 ,  H03K5/24

CPC分类号： G11C27/026 ,  H03K5/249

摘要： Auto-zeroing clocking signals, a first auto-zeroing clocking signal of comparatively-low frequency and duty cycle and a second auto-zeroing clocking signal of the same comparatively-low frequency but complementary and comparatively-high duty cycle, and a sampling clocking signal of comparatively-high frequency respectively initiate auto-zeroing of a circuit element subject to output offset error and data sampling of an A.C. input signal to a latch. The sampling of the A.C. input signal to the latch occurs at the comparatively-high frequency of the clocking signal during the "on" time of the comparatively-high duty cycle second auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide higher speed sampling than heretofore possible. The auto-zeroing of the circuit element subject to input offset error occurs during the "on" time of the comparatively-low duty cycle first auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide lower power sampling than heretofore possible. Typically, the circuit element is either an analog comparator or an operational amplifier, and the sampling circuit of the invention has exemplary utility in analog-to-digital (A/D) conversion.

摘要翻译： 自动归零时钟信号，具有相对较低频率和占空比的第一自动归零时钟信号和具有相同较低频率但互补且相对较高占空比的相同低自适应时钟信号，以及采样时钟信号 相对高的频率分别启动电路元件的自动归零，该电路元件受到输出偏移误差的影响，并将AC输入信号的数据采样到锁存器。 在较低频率的比较高占空比的第二自动归零时钟信号的“接通”时间内，对锁存器的AC输入信号的采样发生在时钟信号的较高频率处，从而能够提供更高的 速度采样比以前可能。 受到输入偏移误差的电路元件的自动归零发生在相对低频率的相对低的占空比第一自动归零时钟信号的“导通”时间，从而能够提供比以前更低的功率采样。 通常，电路元件是模拟比较器或运算放大器，并且本发明的采样电路在模数（A / D）转换中具有示例性的用途。

公开(公告)号：US5656952A

公开(公告)日：1997-08-12

申请号：US558010

申请日：1995-11-13

申请人： Kevin J. McCall ,  David Reynolds

发明人： Kevin J. McCall ,  David Reynolds

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/00

CPC分类号： H03K19/018528 ,  H03K19/00384

摘要： According to embodiments of the present invention, a driver circuit, has first and second reference voltage rails for receiving first and second reference voltages, has first and second inputs for receiving an input differential signal and has first and second outputs for providing an output differential signal. The driver circuit comprises a first CMOS transistor, a second CMOS transistor, and first, second and third current sources. Positive voltage levels with respect to ground at the first and second outputs, are within typical acceptable ECL output voltage levels.

摘要翻译： 根据本发明的实施例，驱动电路具有用于接收第一和第二参考电压的第一和第二参考电压轨道，具有用于接收输入差分信号的第一和第二输入端，并具有用于提供输出差分信号的第一和第二输出 。 驱动器电路包括第一CMOS晶体管，第二CMOS晶体管以及第一，第二和第三电流源。 在第一和第二输出处的相对于地面的正电压电平在典型的可接受的ECL输出电压电平范围内。