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1.发明申请Semiconductor Device Using An Aluminum Interconnect To Form Through-Silicon Vias 失效使用铝互连形成通硅通孔的半导体器件公开(公告)号：US20110037143A1
公开(公告)日：2011-02-17
申请号：US12539105
申请日：2009-08-11
IPC分类号： H01L29/92 , H01L23/48 , H01L21/02 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/76895 , H01L23/481 , H01L23/5222 , H01L28/60 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TV to other BEOL interconnects.
摘要翻译： 线的后端（BEOL）的铝横向互连用于在形成于硅衬底中的半导体芯片中限定穿硅通孔的x和y尺寸。 TSV包括形成在基板的表面上的一个或多个铝环，以及基板中的深沟槽，其直径由铝环的直径决定。 环也可以设置有可以形成电容器的导电带。 带子也可用于提供电视与其他BEOL互连的连接。
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2.发明授权Semiconductor device using an aluminum interconnect to form through-silicon vias 失效使用铝互连的半导体器件形成硅通孔公开(公告)号：US08350359B2
公开(公告)日：2013-01-08
申请号：US12539105
申请日：2009-08-11
CPC分类号： H01L21/76898 , H01L21/76895 , H01L23/481 , H01L23/5222 , H01L28/60 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TSV to other BEOL interconnects.
摘要翻译： 线的后端（BEOL）的铝横向互连用于在形成于硅衬底中的半导体芯片中限定穿硅通孔的x和y尺寸。 TSV包括形成在基板的表面上的一个或多个铝环，以及基板中的深沟槽，其直径由铝环的直径决定。 环也可以设置有可以形成电容器的导电带。 带也可用于提供TSV与其他BEOL互连的连接。
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公开(公告)号：US08614115B2
公开(公告)日：2013-12-24
申请号：US12916236
申请日：2010-10-29
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
CPC分类号： H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.
摘要翻译： 光伏太阳能电池器件的制造方法包括以下。 形成具有第一掺杂密度的p-n结。 通过引入第二掺杂密度以形成用于双发射器应用的高掺杂区域来增强p-n结的形成。 高掺杂区域由与p-n结的形成集成的掩模工艺限定，产生高掺杂区域的掩模图案。 根据高掺杂区域的掩模图案发生高掺杂区域的金属化。
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公开(公告)号：US20110100453A1
公开(公告)日：2011-05-05
申请号：US12915985
申请日：2010-10-29
申请人： Lawrence A. Clevenger , Rainer K. Krause , Zhengwen O. Li , Kevin S. Petrarca , Roger A. Quon , Carl Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Rainer K. Krause , Zhengwen O. Li , Kevin S. Petrarca , Roger A. Quon , Carl Radens , Brian C. Sapp
IPC分类号： H01L31/0224 , H01L31/18
CPC分类号： H01L31/02164 , H01L31/022425 , Y02E10/50
摘要： A method for manufacturing one or more electrically contactable grids on at least one surface of a semiconductor substrate for use in a solar cell product includes the following. A heat-sensitive masking agent layer is deposited on the surface of the substrate of the solar cell product. The masking agent layer is locally heated to form a grid mask. Selected parts of the masking agent layer defined by locally heating are removed to form openings in the grid mask. A contact metallization is applied on the grid mask.
摘要翻译： 一种用于在太阳能电池产品中使用的半导体衬底的至少一个表面上制造一个或多个电接触网格的方法包括以下。 在太阳能电池产品的基板的表面上沉积热敏屏蔽剂层。 掩蔽剂层被局部加热以形成栅格掩模。 去除由局部加热限定的掩蔽剂层的选定部分，以在网格掩模中形成开口。 在栅格掩模上施加接触金属化。
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公开(公告)号：US08574950B2
公开(公告)日：2013-11-05
申请号：US12915985
申请日：2010-10-29
申请人： Lawrence A. Clevenger , Rainer K. Krause , Zhengwen O. Li , Kevin S. Petrarca , Roger A. Quon , Carl Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Rainer K. Krause , Zhengwen O. Li , Kevin S. Petrarca , Roger A. Quon , Carl Radens , Brian C. Sapp
IPC分类号： H01L21/44
CPC分类号： H01L31/02164 , H01L31/022425 , Y02E10/50
摘要： A method for manufacturing one or more electrically contactable grids on at least one surface of a semiconductor substrate for use in a solar cell product includes the following. A heat-sensitive masking agent layer is deposited on the surface of the substrate of the solar cell product. The masking agent layer is locally heated to form a grid mask. Selected parts of the masking agent layer defined by locally heating are removed to form openings in the grid mask. A contact metallization is applied on the grid mask.
摘要翻译： 一种用于在太阳能电池产品中使用的半导体衬底的至少一个表面上制造一个或多个电接触网格的方法包括以下。 在太阳能电池产品的基板的表面上沉积热敏屏蔽剂层。 掩蔽剂层被局部加热以形成栅格掩模。 去除由局部加热限定的掩蔽剂层的选定部分，以在网格掩模中形成开口。 在栅格掩模上施加接触金属化。
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公开(公告)号：US20110100443A1
公开(公告)日：2011-05-05
申请号：US12916236
申请日：2010-10-29
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
IPC分类号： H01L31/06 , H01L31/0236
CPC分类号： H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.
摘要翻译： 光伏太阳能电池器件的制造方法包括以下。 形成具有第一掺杂密度的p-n结。 通过引入第二掺杂密度以形成用于双发射器应用的高掺杂区域来增强p-n结的形成。 高掺杂区域由与p-n结的形成集成的掩模工艺限定，产生高掺杂区域的掩模图案。 根据高掺杂区域的掩模图案发生高掺杂区域的金属化。
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公开(公告)号：US08304912B2
公开(公告)日：2012-11-06
申请号：US12054644
申请日：2008-03-25
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译： 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。
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8.发明授权Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same 有权具有反相源极/漏极金属触点的场效应晶体管（FETS）及其制造方法公开(公告)号：US07659160B2
公开(公告)日：2010-02-09
申请号：US11923075
申请日：2007-10-24
申请人： Michael P. Belyansky , Dureseti Chidambarrao , Lawrence A. Clevenger , Kaushik A. Kumar , Carl Radens
发明人： Michael P. Belyansky , Dureseti Chidambarrao , Lawrence A. Clevenger , Kaushik A. Kumar , Carl Radens
IPC分类号： H01L21/8238
CPC分类号： H01L21/76804 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.
摘要翻译： 本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。 倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。 优选地，反相源极/漏极金属触点的下部具有约0.03mum2至约3.15mum2的横截面积，并且这种反向的源极/漏极金属触点与FET的栅电极间隔开一个 距离范围从约0.001毫米到约5毫米。
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公开(公告)号：US20090117360A1
公开(公告)日：2009-05-07
申请号：US11933760
申请日：2007-11-01
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Habib Hichri , Louis L. Hsu , Kaushik A. Kumar , Carl Radens , Shahab Siddiqui , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Habib Hichri , Louis L. Hsu , Kaushik A. Kumar , Carl Radens , Shahab Siddiqui , Chih-Chao Yang
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y30/00 , H01L21/0338
摘要： A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features of nanometer scale, including at least one recessed region having a nanoscale dimension is formed in the polymeric resist. The top surface of the polymeric resist is modified for enhanced etch resistance by an exposure to an energetic beam, which allows the top surface of the patterned polymeric resist to become more resistant to etching processes and chemistries. The enhanced ratio of etch resistance between the two types of surfaces provides improved image contrast and fidelity between areas having the top surface and the at least one recessed region.
摘要翻译： 含有至少两个不混溶的聚合物嵌段组分的非光敏聚合物抗蚀剂沉积在平面上。 将非光敏聚合物抗蚀剂退火以允许不相容组分的相分离并显影以除去至少两种聚合物嵌段组分中的至少一种。 在聚合物抗蚀剂中形成纳米尺度特征，即纳米尺度的特征，包括具有纳米级尺寸的至少一个凹陷区域。 聚合物抗蚀剂的顶表面通过暴露于能量束而被改进以提高耐蚀刻性，这允许图案化聚合物抗蚀剂的顶表面变得更耐蚀刻工艺和化学物质。 两种类型表面之间的增强的耐蚀刻比提供了改善的图像对比度和具有顶表面和至少一个凹陷区域的区域之间的保真度。
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公开(公告)号：US07514271B2
公开(公告)日：2009-04-07
申请号：US11694183
申请日：2007-03-30
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A method of forming a magnetic domain wall memory apparatus with write/read capability includes forming a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location: forming a magnetic read element associated with each of the shift register structures: and forming a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of one of the plurality of discontinuities in the associated shift register structure.
摘要翻译： 形成具有写入/读取能力的磁畴壁存储装置的方法包括形成多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个 其中的不连续性以便于域壁位置：形成与每个移位寄存器结构相关联的磁读取元件;以及形成与每个移位寄存器结构相关联的磁写元件，所述磁写入元件还包括具有收缩的写入线 其中，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续之一的位置相对应的点处。
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