公开(公告)号：US20230186991A1

公开(公告)日：2023-06-15

申请号：US18106520

申请日：2023-02-07

Applicant: Kioxia Corporation

Inventor： Kenrou KIKUCHI ,  Yasuhiro SHIMURA

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C11/56 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/08 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/30 ,  G11C11/5628 ,  G11C16/24

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

公开(公告)号：US20210074359A1

公开(公告)日：2021-03-11

申请号：US17004272

申请日：2020-08-27

Applicant: Kioxia Corporation

Inventor： Kenrou KIKUCHI ,  Yasuhiro SHIMURA

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C11/56

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

公开(公告)号：US20240203498A1

公开(公告)日：2024-06-20

申请号：US18591563

申请日：2024-02-29

Applicant: KIOXIA CORPORATION

Inventor： Kenrou KIKUCHI ,  Yasuhiro SHIMURA

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

公开(公告)号：US20210295919A1

公开(公告)日：2021-09-23

申请号：US17004680

申请日：2020-08-27

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro SHIMURA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  H01L25/065 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor storage device includes first and second memory strings, a word line, first and second select gate lines, and a control circuit. The first memory string includes a first memory transistor and a first select transistor. The second memory string includes a second memory transistor and a second select transistor. The word line is connected to the first and second memory transistors. The control circuit is connected to the word line and the first and second select gate lines. The control circuit is configured to perform, during a write sequence, a program operation on each of the first and second memory transistors in turn and a verify operation on only one of the first and second memory transistors.

公开(公告)号：US20210193239A1

公开(公告)日：2021-06-24

申请号：US17011747

申请日：2020-09-03

Applicant: KIOXIA CORPORATION

Inventor： Shinji SUZUKI ,  Yasuhiro SHIMURA

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes memory cells a controller performing a write operation on the memory cells. The write operation includes program loops with a program operation and a verification operation. In a first loop the controller applies a first program voltage and a first verification voltage. Next, a detection operation counts the memory cells with a threshold voltage above a first threshold value. In a second program loop, after the detection operation, the controller applies a second program voltage and a second verification voltage. The values of used for second program voltage and the second verification voltage are set dependent on the counted number of memory cells with a threshold voltage above the first threshold value.