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公开(公告)号：US20210312992A1
公开(公告)日：2021-10-07
申请号：US17183805
申请日：2021-02-24
Applicant: KIOXIA CORPORATION
Inventor： Mario SAKO
Abstract: A semiconductor storage device includes a bit line, a memory cell transistor electrically connected to the bit line, and a sense amplifier that reads data from the memory cell transistor via the bit line. During an operation of determining first data and second data, while continuously applying a first voltage to a gate of the memory cell transistor, the sense amplifier first determines the first data based upon a second voltage, and then determines the second data based upon a third voltage lower than the second voltage.
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公开(公告)号：US20240038305A1
公开(公告)日：2024-02-01
申请号：US18485630
申请日：2023-10-12
Applicant: Kioxia Corporation
Inventor： Mai SHIMIZU , Koji KATO , Yoshihiko KAMATA , Mario SAKO
CPC classification number: G11C16/08 , G11C16/30 , G11C16/26 , G11C16/0483 , G11C11/5642 , G11C16/24 , G11C16/32 , G11C16/3427
Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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公开(公告)号：US20230178152A1
公开(公告)日：2023-06-08
申请号：US18161274
申请日：2023-01-30
Applicant: Kioxia Corporation
Inventor： Mai SHIMIZU , Koji KATO , Yoshihiko KAMATA , Mario SAKO
CPC classification number: G11C16/08 , G11C11/5642 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/0483 , G11C16/3427
Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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公开(公告)号：US20220139467A1
公开(公告)日：2022-05-05
申请号：US17575554
申请日：2022-01-13
Applicant: KIOXIA CORPORATION
Inventor： Kosuke YANAGIDAIRA , Mario SAKO
Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through the second and third transistors.
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公开(公告)号：US20210090661A1
公开(公告)日：2021-03-25
申请号：US16902145
申请日：2020-06-15
Applicant: KIOXIA CORPORATION
Inventor： Mario SAKO
Abstract: According to one embodiment, a semiconductor memory device includes: a first bit line; a first memory cell electrically coupled to the first bit line; and a first sense amplifier configured to sense and store data read out to the first bit line. The first sense amplifier includes a first latch circuit and a second latch circuit. In a program operation, each of the first and second latch circuits stores any one bit of program data. In a first verify operation, data is exchanged between the first latch circuit and the second latch circuit when performing the first verify operation for a first data.
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Patent Agency Ranking
公开(公告)号：US20210065774A1
公开(公告)日：2021-03-04
申请号：US16807078
申请日：2020-03-02
Applicant: KIOXIA CORPORATION
Inventor： Keita KIMURA , Kenri NAKAI , Mario SAKO
IPC: G11C11/4076 , G11C11/4074 , G11C11/4091 , G11C11/4094 , G11C11/408 , G11C7/10 , G11C7/22
Abstract: A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.
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公开(公告)号：US20240420765A1
公开(公告)日：2024-12-19
申请号：US18818527
申请日：2024-08-28
Applicant: Kioxia Corporation
Inventor： Mai SHIMIZU , Koji KATO , Yoshihiko KAMATA , Mario SAKO
Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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公开(公告)号：US20230260579A1
公开(公告)日：2023-08-17
申请号：US18305654
申请日：2023-04-24
Applicant: Kioxia Corporation
Inventor： Kosuke YANAGIDAIRA , Mario SAKO
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C11/5671 , G11C16/30 , G11C11/5642 , G11C16/24
Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.
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公开(公告)号：US20240087656A1
公开(公告)日：2024-03-14
申请号：US18332753
申请日：2023-06-12
Applicant: Kioxia Corporation
Inventor： Katsuaki ISOBE , Takeshi HIOKA , Mario SAKO
CPC classification number: G11C16/26 , G11C16/0483
Abstract: A semiconductor memory device includes a first memory cell transistor, a first bit line electrically coupled to the first memory cell transistor, a first sense amplifier, and a first latch circuit. The first sense amplifier includes a first node coupled to the first bit line, a first transistor including one end electrically coupled to the first latch circuit, a second node coupled to a gate of the first transistor, and a second transistor coupled between the first and second nodes. The second transistor is in an ON state during an operation of transferring a charge from the first bit line to the first and second nodes in accordance with data of the first memory cell transistor. The second transistor is in an OFF state during an operation of transferring data of the second node to the first latch circuit.
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公开(公告)号：US20220246197A1
公开(公告)日：2022-08-04
申请号：US17349106
申请日：2021-06-16
Applicant: Kioxia Corporation
Inventor： Mario SAKO
IPC: G11C11/4091 , G11C11/4094 , G11C11/4074 , G11C11/4096 , G11C11/4076 , G11C5/06
Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, and a sense amplifier. The sense amplifier includes: a first node configured to be electrically coupled to the bit line; a first transistor in which a gate is coupled to the first node, and which is configured to be coupled to a second node; a second transistor configured to couple the second node and a third node; and a third transistor in which a gate is coupled to the third node, and which is configured to be coupled to the first node. The sense amplifier applies a second voltage obtained by amplifying a first voltage of the first node to the third node, and applies a third voltage obtained by amplifying the second voltage to the first node.
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