公开(公告)号：US20240038305A1

公开(公告)日：2024-02-01

申请号：US18485630

申请日：2023-10-12

Applicant: Kioxia Corporation

Inventor： Mai SHIMIZU ,  Koji KATO ,  Yoshihiko KAMATA ,  Mario SAKO

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/0483 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/32 ,  G11C16/3427

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US20230178152A1

公开(公告)日：2023-06-08

申请号：US18161274

申请日：2023-01-30

Applicant: Kioxia Corporation

Inventor： Mai SHIMIZU ,  Koji KATO ,  Yoshihiko KAMATA ,  Mario SAKO

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/08 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/0483 ,  G11C16/3427

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US20210383868A1

公开(公告)日：2021-12-09

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki SHIMIZU ,  Yoshihiko KAMATA ,  Tsukasa KOBAYASHI ,  Hideyuki KATAOKA ,  Koji KATO ,  Takumi FUJIMOTO ,  Yoshinao SUZUKI ,  Yuui SHIMIZU

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US20220310180A1

公开(公告)日：2022-09-29

申请号：US17807034

申请日：2022-06-15

Applicant: KIOXIA CORPORATION

Inventor： Yoshihiko KAMATA ,  Naofumi ABIKO

IPC: G11C16/34 ,  G11C11/4094 ,  G11C7/12 ,  G11C16/04 ,  G11C11/56 ,  G11C16/32 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.

公开(公告)号：US20240420765A1

公开(公告)日：2024-12-19

申请号：US18818527

申请日：2024-08-28

Applicant: Kioxia Corporation

Inventor： Mai SHIMIZU ,  Koji KATO ,  Yoshihiko KAMATA ,  Mario SAKO

IPC: G11C16/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US20240029805A1

公开(公告)日：2024-01-25

申请号：US18482103

申请日：2023-10-06

Applicant: KIOXIA CORPORATION

Inventor： Yoshihiko KAMATA ,  Naofumi ABIKO

IPC: G11C16/34 ,  G11C11/4094 ,  G11C7/12 ,  G11C16/04 ,  G11C11/56 ,  G11C16/32 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/3445 ,  G11C11/4094 ,  G11C16/3459 ,  G11C7/12 ,  G11C16/0475 ,  G11C16/0483 ,  G11C11/5635 ,  G11C16/32 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C2211/5641 ,  G11C8/08

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.