公开(公告)号：US5426326A

公开(公告)日：1995-06-20

申请号：US103206

申请日：1993-08-09

申请人： Kiyonori Ohyu ,  Kozo Watanabe ,  Osamu Tsuchiya ,  Kazuyoshi Oshima ,  Yoshifumi Kawamoto ,  Atsushi Hiraiwa ,  Takashi Nishida

发明人： Kiyonori Ohyu ,  Kozo Watanabe ,  Osamu Tsuchiya ,  Kazuyoshi Oshima ,  Yoshifumi Kawamoto ,  Atsushi Hiraiwa ,  Takashi Nishida

IPC分类号： H01L27/10 ,  H01L29/08 ,  H01L29/36 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/0847 ,  H01L29/08 ,  H01L29/36

摘要： An arrangement is provided to decrease the junction degradation caused by the leakage current at a p-n junction in semiconductor devices. This arrangement can be useful for a variety of devices, and is especially effective for reducing junction degradation at the source or drain region of a MOSFET. To achieve such a reduction, a p-n junction layer is provided at a p-n junction of a semiconductor region and a substrate. Carrier concentration distributions of a p-type layer and an n-type layer of the p-n junction layer are set so that an electric field which tends to be increased by a local electric field enhancement in a depletion layer of the p-n junction due to a precipitate introduced from a semiconductor surface will not exceed 1 MV/cm. When the depth of a depletion layer of the p-type layer or the n-type layer is referred to as Xp or Xn, and the slope of the carrier concentration, Ap or An, the following relation is provided:4.3.times.10.sup.12 (/cm.sup.2).gtoreq.An.multidot.Xn.sup.2 =Ap.multidot.Xp.sup.2Preferably, the p-n junction layer is formed under a contact hole of a source or drain region if the device in question is a MOSFET. As a result of using this arrangement, the leakage current caused by a local Zener effect decreases so that the electric field locally increased by the precipitate will not be greater than 1 MV/cm.

摘要翻译： 提供了一种布置，以减少由半导体器件中的p-n结处的漏电流引起的结劣化。 这种布置对于各种器件可能是有用的，并且对于降低MOSFET的源极或漏极区域处的结退化特别有效。 为了实现这种减少，在半导体区域和衬底的p-n结处提供p-n结层。 pn结层的p型层和n型层的载流子浓度分布被设定为使得由于沉淀引起的在pn结的耗尽层中的局部电场增强倾向于增加的电场 从半导体表面引入的电流不超过1MV / cm。 当p型层或n型层的耗尽层的深度被称为Xp或Xn以及载流子浓度Ap或An的斜率时，提供以下关系：4.3×10 12（/ cm 2） ）> / = AnxXn2 = ApxXp2如果所讨论的器件是MOSFET，则优选地，在源极或漏极区域的接触孔下方形成pn结层。 作为使用这种布置的结果，由局部齐纳效应引起的漏电流减小，使得由沉淀物局部增加的电场将不会大于1MV / cm。

公开(公告)号：US07081649B2

公开(公告)日：2006-07-25

申请号：US10920389

申请日：2004-08-18

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn 1和Q n 2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp 1中，形成高密度N型半导体区域16和16b，以及 高密度P型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06743673B2

公开(公告)日：2004-06-01

申请号：US10145810

申请日：2002-05-16

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US20050017274A1

公开(公告)日：2005-01-27

申请号：US10920389

申请日：2004-08-18

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06800888B2

公开(公告)日：2004-10-05

申请号：US10759238

申请日：2004-01-20

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L2976

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

公开(公告)号：US06503794B1

公开(公告)日：2003-01-07

申请号：US09381345

申请日：1999-09-20

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster. In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes is formed the first side wall spacer 14 composed of silicon nitride and the second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and are formed connecting portion connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area are formed high density N-type semiconductor areas 16 and 16b, as well as a high density P-type semiconductor area 17 in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 本发明的一个目的是提供一种半导体集成电路的技术，该技术允许每个DRAM存储器单元被细分，以便更高集成度和更快地运行。 在本发明的这种半导体集成电路的制造方法中，首先，通过半导体基板1的主面上的栅极绝缘膜6形成栅电极7，在各栅极电极的侧面 形成由氮化硅构成的第一侧壁隔离物14和由氧化硅构成的第二侧壁隔离物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，以相对于第一侧壁隔板14的自匹配方式打开连接孔19和21，并且形成将导体20连接到位线BL的连接部分。 此外，在N沟道MISFET Qn1和Qn2中以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中形成高密度N型半导体区域16和16b，以及高密度P型 半导体区域17相对于第二侧壁间隔件15以自匹配的方式。

公开(公告)号：US20080230845A1

公开(公告)日：2008-09-25

申请号：US11859043

申请日：2007-09-21

申请人： Kensuke Okonogi ,  Kiyonori Ohyu

发明人： Kensuke Okonogi ,  Kiyonori Ohyu

IPC分类号： H01L29/78 ,  H01L23/52 ,  H01L21/4763

CPC分类号： H01L29/7834 ,  H01L21/26506 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76859 ,  H01L23/53271 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.

摘要翻译： 半导体器件可以包括但不限于单晶硅扩散层，多晶硅导体和扩散阻挡层。 扩散阻挡层将多晶硅导体与单晶硅扩散层分离。 扩散阻挡层防止在单晶硅扩散层和多晶硅导体之间的硅间隙和硅空位中的至少一个的扩散。

公开(公告)号：US07186632B2

公开(公告)日：2007-03-06

申请号：US10395724

申请日：2003-03-24

申请人： Kazuo Ogawa ,  Kiyonori Ohyu ,  Kensuke Okonogi ,  Toshihiro Imamura ,  Keiichi Watanabe ,  Hiroyuki Ohta

发明人： Kazuo Ogawa ,  Kiyonori Ohyu ,  Kensuke Okonogi ,  Toshihiro Imamura ,  Keiichi Watanabe ,  Hiroyuki Ohta

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28247 ,  H01L21/28061

摘要： In a method for manufacturing a semiconductor device having a laminated gate electrode, a phosphorus-doped polysilicon is formed on a gate oxide film. A high-melting metal or a compound of a high-melting metal and silicon is formed on the polysilicon. Phosphorus is doped into the polysilicon so that a concentration of the phosphorus in the polysilicon at an interface between the polysilicon and the gate oxide film is 2×1020(1/cm3) or less. Then, thermal oxidation is carried out in a wet-hydrogen atmosphere containing water vapor.

摘要翻译： 在具有层叠栅电极的半导体器件的制造方法中，在栅极氧化膜上形成磷掺杂多晶硅。 在多晶硅上形成高熔点金属或高熔点金属和硅的化合物。 将磷掺杂到多晶硅中，使得多晶硅和栅极氧化物膜之间的界面处的多晶硅中的磷的浓度为2×10 20（1 / cm 3） 或更少。 然后，在含有水蒸气的湿氢气氛中进行热氧化。

公开(公告)号：US07737505B2

公开(公告)日：2010-06-15

申请号：US11859043

申请日：2007-09-21

申请人： Kensuke Okonogi ,  Kiyonori Ohyu

发明人： Kensuke Okonogi ,  Kiyonori Ohyu

IPC分类号： H01L29/78 ,  H01L23/52

CPC分类号： H01L29/7834 ,  H01L21/26506 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76859 ,  H01L23/53271 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.

摘要翻译： 半导体器件可以包括但不限于单晶硅扩散层，多晶硅导体和扩散阻挡层。 扩散阻挡层将多晶硅导体与单晶硅扩散层分离。 扩散阻挡层防止在单晶硅扩散层和多晶硅导体之间的硅间隙和硅空位中的至少一个的扩散。

公开(公告)号：US07700431B2

公开(公告)日：2010-04-20

申请号：US11153321

申请日：2005-06-16

申请人： Kensuke Okonogi ,  Kiyonori Ohyu ,  Kazutaka Manabe ,  Satoru Yamada ,  Takuo Ohashi

发明人： Kensuke Okonogi ,  Kiyonori Ohyu ,  Kazutaka Manabe ,  Satoru Yamada ,  Takuo Ohashi

IPC分类号： H01L21/8242 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76877 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66575

摘要： A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.

摘要翻译： 一种用于在硅衬底上制造DRAM器件的方法包括：在存储单元区域中形成单元晶体管和在外围电路区域中形成其它晶体管; 形成连接到所述单元晶体管的扩散区域的多晶硅插塞和连接到所述另一晶体管的扩散区域的金属插塞; 在980〜1020℃的温度下进行热处理。 在700〜850℃的温度下进行热处理。 将氟或氟化硼注入其他晶体管的扩散区域; 并在500〜850℃的温度下进行热处理。