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公开(公告)号：US20060127568A1
公开(公告)日：2006-06-15
申请号：US10542846
申请日：2004-01-20
IPC分类号： B05D5/12
CPC分类号： H05K1/0306 , H01L23/15 , H01L23/49822 , H01L2924/0002 , H05K3/4611 , H05K3/4629 , H05K2201/0187 , H01L2924/00
摘要： A plurality of first green sheets forming first ceramic layers after firing are stacked to form a first pre-fired substrate 4. Next, a plurality of second green sheets forming second ceramic layers after firing are stacked to form a second pre-fired substrate. Next, the first pre-fired substrate 4 is formed with recesses 10. Next, first pre-fired blocks 6 of sizes fitting into the recesses are formed from the second pre-fired substrate. The first pre-fired blocks 6 are fit into the recesses 10 so that the stacking direction A of the first green sheets and the stacking direction A′ of the second green sheets become the same. The first pre-fired substrate 4 in which the first pre-fired blocks 6 are fit is fired.
摘要翻译： 在烧成后形成第一陶瓷层的多个第一生片层叠，形成第一预烧基板4。 接下来，堆叠在焙烧后形成第二陶瓷层的多个第二生片，以形成第二预烧基板。 接下来，第一预烧基板4形成有凹部10。 接下来，由第二预烧基板形成装配到凹部中的尺寸的第一预烧块6。 第一预烧块6装配到凹部10中，使得第一生坯的堆叠方向A和第二生坯的层叠方向A'变得相同。 烧制第一预烧块6的第一预烧基板4。
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公开(公告)号：US20050189137A1
公开(公告)日：2005-09-01
申请号：US11059585
申请日：2005-02-17
IPC分类号： C04B35/622 , C04B35/00 , C04B35/495 , H01G4/06 , H01G4/20 , H05K1/03 , H05K1/09 , H05K1/16 , H05K3/00 , H05K3/46
CPC分类号： H05K1/162 , H05K1/0306 , H05K3/005 , H05K3/4611 , H05K3/4629 , H05K2201/0187 , Y10T29/49155 , Y10T29/49162 , Y10T29/49163 , Y10T29/49165 , Y10T156/1056 , Y10T156/1057 , Y10T428/24322
摘要： An object of the invention is to connect different dielectrics electrically to each other in the direction of main surface of a sheet in a multilayer ceramic substrate and to increase the degree of flexibility in design and make the multilayer ceramic substrate compact in size. A multilayer ceramic substrate in accordance with the invention is formed of a plurality of laminated ceramic substrates including such a composite ceramic substrate of different materials that is made by inserting the second ceramic substrate in a pounched-out portion made in the first ceramic substrate and by planarizing its top and bottom surfaces, wherein a conductive layer is formed in a portion across a boundary between the first ceramic substrate and the second ceramic substrate of the interface of the composite ceramic substrate of different materials.
摘要翻译： 本发明的目的是在多层陶瓷基板中的片材的主表面的方向上彼此电连接不同的电介质，并且增加设计的柔性程度，并使多层陶瓷基板的尺寸更小。 根据本发明的多层陶瓷基板由多个层叠陶瓷基板形成，该多个层叠陶瓷基板包括这样的不同材料的复合陶瓷基板，该复合陶瓷基板是通过将第二陶瓷基板插入在第一陶瓷基板中形成的突出部分而形成的， 平面化其顶表面和底表面，其中导电层形成在穿过不同材料的复合陶瓷衬底的界面的第一陶瓷衬底和第二陶瓷衬底之间的边界的部分中。
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公开(公告)号：US07243424B2
公开(公告)日：2007-07-17
申请号：US11059585
申请日：2005-02-17
IPC分类号： H01K3/10
CPC分类号： H05K1/162 , H05K1/0306 , H05K3/005 , H05K3/4611 , H05K3/4629 , H05K2201/0187 , Y10T29/49155 , Y10T29/49162 , Y10T29/49163 , Y10T29/49165 , Y10T156/1056 , Y10T156/1057 , Y10T428/24322
摘要： An object of the invention is to connect different dielectrics electrically to each other in the direction of main surface of a sheet in a multilayer ceramic substrate and to increase the degree of flexibility in design and make the multilayer ceramic substrate compact in size. A multilayer ceramic substrate in accordance with the invention is formed of a plurality of laminated ceramic substrates including such a composite ceramic substrate of different materials that is made by inserting the second ceramic substrate in a pounched-out portion made in the first ceramic substrate and by planarizing its top and bottom surfaces, wherein a conductive layer is formed in a portion across a boundary between the first ceramic substrate and the second ceramic substrate of the interface of the composite ceramic substrate of different materials.
摘要翻译： 本发明的目的是在多层陶瓷基板中的片材的主表面的方向上彼此电连接不同的电介质，并且增加设计的柔性程度，并使多层陶瓷基板的尺寸更小。 根据本发明的多层陶瓷基板由多个层叠陶瓷基板形成，该多个层叠陶瓷基板包括这样的不同材料的复合陶瓷基板，该复合陶瓷基板是通过将第二陶瓷基板插入在第一陶瓷基板中形成的突出部分而形成的， 平面化其顶表面和底表面，其中导电层形成在穿过不同材料的复合陶瓷衬底的界面的第一陶瓷衬底和第二陶瓷衬底之间的边界的部分中。
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公开(公告)号：US20070110956A1
公开(公告)日：2007-05-17
申请号：US11622795
申请日：2007-01-12
IPC分类号： B32B3/10
CPC分类号： H05K1/162 , H05K1/0306 , H05K3/005 , H05K3/4611 , H05K3/4629 , H05K2201/0187 , Y10T29/49155 , Y10T29/49162 , Y10T29/49163 , Y10T29/49165 , Y10T156/1056 , Y10T156/1057 , Y10T428/24322
摘要： An object of the invention is to connect different dielectrics electrically to each other in the direction of main surface of a sheet in a multilayer ceramic substrate and to increase the degree of flexibility in design and make the multilayer ceramic substrate compact in size. A multilayer ceramic substrate in accordance with the invention is formed of a plurality of laminated ceramic substrates including such a composite ceramic substrate of different materials that is made by inserting the second ceramic substrate in a pounched-out portion made in the first ceramic substrate and by planarizing its top and bottom surfaces, wherein a conductive layer is formed in a portion across a boundary between the first ceramic substrate and the second ceramic substrate of the interface of the composite ceramic substrate of different materials.
摘要翻译： 本发明的目的是在多层陶瓷基板中的片材的主表面的方向上彼此电连接不同的电介质，并且增加设计的柔性程度，并使多层陶瓷基板的尺寸更小。 根据本发明的多层陶瓷基板由多个层叠陶瓷基板形成，该多个层叠陶瓷基板包括这样的不同材料的复合陶瓷基板，该复合陶瓷基板是通过将第二陶瓷基板插入在第一陶瓷基板中形成的突出部分而形成的， 平面化其顶表面和底表面，其中导电层形成在穿过不同材料的复合陶瓷衬底的界面的第一陶瓷衬底和第二陶瓷衬底之间的边界的部分中。
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公开(公告)号：US07155816B2
公开(公告)日：2007-01-02
申请号：US10354972
申请日：2003-01-31
IPC分类号： H05K3/36
CPC分类号： H01L23/15 , H01L23/13 , H01L23/49822 , H01L23/642 , H01L23/645 , H01L2924/0002 , H01L2924/09701 , H01L2924/15153 , H01L2924/1517 , H01L2924/3011 , H05K1/0306 , H05K1/162 , H05K1/165 , H05K1/183 , H05K3/4611 , H05K3/4629 , H05K3/4697 , H05K2203/063 , Y10T29/43 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49833 , Y10T428/252 , H01L2924/00
摘要： A method for producing a multilayer ceramic substrate having a cavity formed therein includes punching a through opening corresponding to the cavity in green sheets constituting a laminate, and printing a conductor at a predetermined position of the green sheets, laminating the green sheets to constitute a green sheet laminate, and applying a pressure to the green sheet laminate by using a compression member having a projection at a position corresponding to the cavity to thereby compress the green sheet laminate. The projection has a height which is equal to the depth of the cavity multiplied by compression ratio of the green sheet laminate, and the green sheet laminate is compressed by applying the pressure such that compression ratio of the bottom of the cavity is identical with the compression ratio of other parts of the green sheet laminate.
摘要翻译： 一种具有形成有空腔的多层陶瓷基板的制造方法，其特征在于，在构成层叠体的生片中冲压与所述空腔对应的通孔，在所述生片的规定位置印刷导体，层叠所述生片以构成绿色 并且通过使用在与空腔相对应的位置处具有突起的压缩构件对生片层压体施加压力，从而压缩生片层压体。 突起的高度等于生坯片层压体的压缩比与腔的深度相乘，并且通过施加压力使生坯片层压体压缩，使得腔的底部的压缩比与压缩相同 生片层压板的其他部分的比例。
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6.发明授权Low dielectric polymer and film, substrate and electronic part using the same 失效低介电聚合物和薄膜，基板和电子部件使用相同
公开(公告)号：US5914283A
公开(公告)日：1999-06-22
申请号：US790431
申请日：1997-01-29
申请人： Toshiaki Yamada , Takeshi Takahashi , Atsushi Yakuwa , Hideaki Ninomiya , Naoyuki Amaya , Naoki Saito , Yasuhiro Imamura , Norihiro Kaiya
发明人： Toshiaki Yamada , Takeshi Takahashi , Atsushi Yakuwa , Hideaki Ninomiya , Naoyuki Amaya , Naoki Saito , Yasuhiro Imamura , Norihiro Kaiya
CPC分类号： H01B3/448 , H05K1/0326 , Y10T428/268 , Y10T428/269 , Y10T428/31935 , Y10T428/31938 , Y10T442/2475 , Y10T442/2934 , Y10T442/2992
摘要： A film comprises glass fiber impregnated with a low dielectric polymer obtained by polymerizing a monomeric composition comprising a fumaric acid diester monomer and optionally a vinyl monomer. The polymer having a low dielectric constant and reduced dielectric loss is used as an electrically insulating material in a high frequency band of at least 500 MHz.
摘要翻译： 薄膜包括浸渍有低介电聚合物的玻璃纤维，该低介电聚合物通过聚合包含富马酸二酯单体和任选的乙烯基单体的单体组合物而获得。 具有低介电常数和降低介电损耗的聚合物用作至少500MHz的高频带中的电绝缘材料。
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公开(公告)号：US07800168B2
公开(公告)日：2010-09-21
申请号：US11833401
申请日：2007-08-03
申请人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
发明人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
IPC分类号： H01L29/76
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/083 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.
摘要翻译： 半导体器件包括第一导电类型的基底层，形成在基底层上的第一导电类型的阻挡层，从阻挡层的表面形成的沟槽到达达到 阻挡层和基底层之间的界面，通过栅极绝缘膜形成在沟槽中的栅极电极，选择性地形成在阻挡层的表面部分中的第二导电类型的接触层，第一导电性的源极层 形成在所述阻挡层的表面部分中以与所述沟槽中的所述接触层和所述栅极绝缘膜的侧壁接触的第一主电极以及与所述接触层和所述源极层接触的第一主电极。
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公开(公告)号：US07319257B2
公开(公告)日：2008-01-15
申请号：US11626141
申请日：2007-01-23
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译： 功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。 在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。 在虚拟电池中设置第二导电类型的缓冲层。 栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。 具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。 虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。
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公开(公告)号：US20070114570A1
公开(公告)日：2007-05-24
申请号：US11626141
申请日：2007-01-23
IPC分类号： H01L31/00
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译： 功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。 在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。 在虚拟电池中设置第二导电类型的缓冲层。 栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。 具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。 虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。
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公开(公告)号：US20060113613A1
公开(公告)日：2006-06-01
申请号：US11331160
申请日：2006-01-13
申请人： Hideaki Ninomiya , Tomoki Inoue
发明人： Hideaki Ninomiya , Tomoki Inoue
IPC分类号： H01L29/76
CPC分类号： H01L29/404 , H01L29/0619 , H01L29/0692 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.
摘要翻译： 本文公开的半导体器件包括：第一导电类型的第一基极区; 第二基极区域，其具有第二导电类型并且选择性地形成在所述第一基极区域的主表面上; 阻挡区域，其具有第一导电类型并且形成在第一基底区域的主表面上，止挡区域距第二基底区域预定距离并且围绕第二基底区域; 以及形成在所述第二基极区域和所述阻挡区域之间的所述第一基底区域的主表面上的第二导电类型的环形区域，所述环形区域围绕所述第二基极区域螺旋地且与所述第二基底区域电连接 区域和止挡区域。
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