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公开(公告)号：US08357963B2
公开(公告)日：2013-01-22
申请号：US13185965
申请日：2011-07-19
申请人： Kiyoshi Kato , Takanori Matsuzaki
发明人： Kiyoshi Kato , Takanori Matsuzaki
IPC分类号： H01L27/108
CPC分类号： H01L27/11521 , H01L27/108 , H01L27/11524 , H01L27/11551 , H01L27/1156 , H01L27/1225
摘要： A semiconductor device includes a material with which off-state current of a transistor can be sufficiently small; for example, an oxide semiconductor material is used. Further, transistors of memory cells of the semiconductor device, which include an oxide semiconductor material, are connected in series. Further, the same wiring (the j-th word line (j is a natural number greater than or equal to 2 and less than or equal to m)) is used as a wiring electrically connected to one of terminals of a capacitor of the j-th memory cell and a wiring electrically connected to a gate terminal of a transistor, in which a channel is formed in an oxide semiconductor layer, of the (j−1)-th memory cell. Therefore, the number of wirings per memory cell and the area occupied by one memory cell are reduced.
摘要翻译： 半导体器件包括晶体管的截止电流足够小的材料; 例如，使用氧化物半导体材料。 此外，包括氧化物半导体材料的半导体器件的存储单元的晶体管串联连接。 此外，使用相同的布线（第j字线（j为大于等于2且小于等于m的自然数））作为与j的电容器的端子之一电连接的布线 第（j-1）个存储单元和与第一第（j-1）个存储单元形成沟道的晶体管的栅极端子电连接的布线。 因此，每个存储单元的布线数和一个存储单元占用的面积减少。
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公开(公告)号：US20120056647A1
公开(公告)日：2012-03-08
申请号：US13221947
申请日：2011-08-31
IPC分类号： H03K17/00
CPC分类号： G11C11/403 , G11C16/0433 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1156 , H01L27/1225 , H01L29/7869
摘要： The semiconductor device includes a memory cell including a first transistor including a first channel formation region, a first gate electrode, and first source and drain regions; a second transistor including a second channel formation region provided so as to overlap with at least part of either of the first source region or the first drain region, a second source electrode, a second drain electrode electrically connected to the first gate electrode, and a second gate electrode; and an insulating layer provided between the first transistor and the second transistor. In a period during which the second transistor needs in an off state, at least when a positive potential is supplied to the first source region or the first drain region, a negative potential is supplied to the second gate electrode.
摘要翻译： 半导体器件包括存储单元，其包括第一晶体管，第一晶体管包括第一沟道形成区，第一栅电极以及第一源区和漏区; 第二晶体管，包括设置成与第一源极区域或第一漏极区域中的至少一部分重叠的第二沟道形成区域，第二源极电极，电连接到第一栅极电极的第二漏极电极，以及 第二栅电极; 以及设置在第一晶体管和第二晶体管之间的绝缘层。 在第二晶体管需要处于截止状态的期间中，至少当向第一源极区域或第一漏极区域提供正电位时，向第二栅电极提供负电位。
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公开(公告)号：US20120033485A1
公开(公告)日：2012-02-09
申请号：US13193966
申请日：2011-07-29
IPC分类号： G11C11/24
CPC分类号： G11C16/0408 , G11C11/405 , G11C11/4076 , G11C11/4087 , H01L27/11521 , H01L27/1156 , H01L27/1207
摘要： In a semiconductor device which includes a bit line, m (m is a natural number of 3 or more) word lines, a source line, m signal lines, first to m-th memory cells, and a driver circuit, the memory cell includes a first transistor and a second transistor for storing electrical charge accumulated in a capacitor, and the second transistor includes a channel formed in an oxide semiconductor layer. In the semiconductor device, the driver circuit generates a signal to be output to a (j−1)th (j is a natural number of 3 or more) signal line with the use of a signal to be output to a j-th signal line.
摘要翻译： 在包括位线的m（m为3以上的自然数）字线，源极线，m条信号线，第1〜第m存储器单元和驱动电路的半导体器件中，所述存储单元包括 第一晶体管和第二晶体管，用于存储积聚在电容器中的电荷，第二晶体管包括形成在氧化物半导体层中的沟道。 在半导体装置中，驱动电路使用要输出到第j信号的信号，生成输出到第（j-1）（j为3以上的自然数）信号线的信号 线。
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公开(公告)号：US08576636B2
公开(公告)日：2013-11-05
申请号：US13175090
申请日：2011-07-01
IPC分类号： G11C11/34
CPC分类号： H01L27/1156 , G11C11/404 , G11C16/0441 , H01L27/1207
摘要： A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first channel formation region. The second transistor includes a second channel formation region. The first channel formation region includes a semiconductor material different from the semiconductor material of the second channel formation region.
摘要翻译： 包括在存储单元阵列中的多个存储单元被分成多个块，每个多行。 公共位线通过块中的选择晶体管电连接到分割位线。 一个存储单元包括第一晶体管，第二晶体管和电容器。 第一晶体管包括第一沟道形成区。 第二晶体管包括第二沟道形成区域。 第一沟道形成区域包括与第二沟道形成区域的半导体材料不同的半导体材料。
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公开(公告)号：US08441841B2
公开(公告)日：2013-05-14
申请号：US13027546
申请日：2011-02-15
IPC分类号： G11C11/24
CPC分类号： G11C8/08 , G11C11/413
摘要： An object is to provide a semiconductor device with a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor and the semiconductor device includes a potential conversion circuit which functions to output a potential lower than a reference potential for reading data from the memory cell. With the use of a widegap semiconductor, a semiconductor device capable of sufficiently reducing the off-state current of a transistor included in a memory cell and capable of holding data for a long time can be provided.
摘要翻译： 目的是提供一种具有新颖结构的半导体器件，其即使在未被供电且具有无限数量的写周期的情况下也可以保存存储的数据。 半导体器件包括具有宽栅半导体例如氧化物半导体的存储单元，并且该半导体器件包括用于输出低于用于从存储单元读取数据的参考电位的电位的电位转换电路。 通过使用宽栅半导体，可以提供能够充分降低包含在存储单元中并能够长时间保持数据的晶体管的截止电流的半导体器件。
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公开(公告)号：US20120051116A1
公开(公告)日：2012-03-01
申请号：US13206547
申请日：2011-08-10
IPC分类号： G11C11/24
CPC分类号： G11C16/0433 , G11C11/404
摘要： A semiconductor device with a novel structure and a driving method thereof are provided. A semiconductor device includes a non-volatile memory cell including a writing transistor including an oxide semiconductor, a reading p-channel transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is written to the memory cell by turning on the writing transistor so that a potential is supplied to a node where a source electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of electric charge is held in the node. In a holding period, the memory cell is brought into a selected state and a source electrode and a drain electrode of the reading transistor are set to the same potential, whereby the electric charge stored in the node is held.
摘要翻译： 提供具有新颖结构的半导体器件及其驱动方法。 一种半导体器件包括：非易失性存储单元，包括包括氧化物半导体的写入晶体管，包括与写入晶体管的半导体材料不同的半导体材料的读取P沟道晶体管，以及电容器。 通过接通写入晶体管将数据写入存储单元，使得电位被提供给写入晶体管的源电极，电容器的一个电极和读取晶体管的栅极电连接的节点，以及 然后关闭写入晶体管，使得节点中保持预定量的电荷。 在保持期间，将存储单元置于选择状态，将读取晶体管的源电极和漏电极设定为相同的电位，由此保存存储在节点中的电荷。
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公开(公告)号：US20110199816A1
公开(公告)日：2011-08-18
申请号：US13022407
申请日：2011-02-07
IPC分类号： G11C11/24
CPC分类号： G11C11/24 , G11C11/403 , G11C11/405 , H01L27/1052 , H01L27/11521 , H01L27/1225
摘要： An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change circuit which selectively applies a potential either equal to or different from a potential of a bit line to a source line. Thus, power consumption of the semiconductor device can be sufficiently reduced.
摘要翻译： 目的在于提供具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且写入的次数不受限制。 半导体器件使用宽间隙半导体形成，并且包括电位改变电路，其选择性地将与位线的电位等于或不同的电位施加到源极线。 因此，可以充分降低半导体器件的功耗。
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公开(公告)号：US20110198593A1
公开(公告)日：2011-08-18
申请号：US13019330
申请日：2011-02-02
IPC分类号： H01L29/772
CPC分类号： H01L27/108 , H01L27/105 , H01L27/1052 , H01L27/1156 , H01L27/1225
摘要： A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.
摘要翻译： 具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且对写入次数没有限制。 在半导体装置中，以矩阵形式设置有各自包括第一晶体管，第二晶体管和电容器的多个存储单元，以及用于将一个存储单元连接到另一个存储单元的源（或称为位线） 第一晶体管的漏极电极通过第二晶体管的源极或漏极电极彼此电连接。 因此，布线数量可以比第一晶体管的源极或漏极以及第二晶体管的源极或漏极连接到不同的布线的情况下的布线数量小。 因此，可以提高半导体器件的集成度。
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公开(公告)号：US20080129396A1
公开(公告)日：2008-06-05
申请号：US11979995
申请日：2007-11-13
申请人： Kiyoshi Kato , Takanori Matsuzaki
发明人： Kiyoshi Kato , Takanori Matsuzaki
IPC分类号： H03L7/08
CPC分类号： H03L7/0995 , H03L7/093 , H03L7/107 , H03L7/18
摘要： An object is to provide a PLL having a wide operating range. Another object is to provide a semiconductor device or a wireless tag which has a wide operating range in a communication distance or temperature by incorporating such a PLL. The semiconductor device or the wireless tag includes a first divider circuit; a second divider circuit; a phase comparator circuit to which an output of the first divider circuit and an output of the second divider circuit are provided; a loop filter to which an output of the phase comparator circuit is supplied and in which a time constant is switched in accordance with an inputted signal; and a voltage controlled oscillator circuit to which an output of the loop filter is supplied and which supplies an output to the second divider circuit.
摘要翻译： 目的是提供具有宽工作范围的PLL。 另一个目的是提供一种半导体器件或无线标签，其通过结合这样的PLL在通信距离或温度中具有宽的工作范围。 半导体器件或无线标签包括第一除法电路; 第二分频电路; 相位比较器电路，第一分频电路的输出和第二除法电路的输出端提供给该相位比较器电路; 环路滤波器，根据输入的信号，提供相位比较器电路的输出并将时间常数切换到该环路滤波器; 以及压控振荡器电路，所述环路滤波器的输出端被提供给所述压控振荡器电路，并将输出提供给所述第二除法电路。
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公开(公告)号：US08654566B2
公开(公告)日：2014-02-18
申请号：US13221947
申请日：2011-08-31
IPC分类号： G11C11/24
CPC分类号： G11C11/403 , G11C16/0433 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1156 , H01L27/1225 , H01L29/7869
摘要： The semiconductor device includes a memory cell including a first transistor including a first channel formation region, a first gate electrode, and first source and drain regions; a second transistor including a second channel formation region provided so as to overlap with at least part of either of the first source region or the first drain region, a second source electrode, a second drain electrode electrically connected to the first gate electrode, and a second gate electrode; and an insulating layer provided between the first transistor and the second transistor. In a period during which the second transistor needs in an off state, at least when a positive potential is supplied to the first source region or the first drain region, a negative potential is supplied to the second gate electrode.
摘要翻译： 半导体器件包括存储单元，其包括第一晶体管，第一晶体管包括第一沟道形成区，第一栅电极以及第一源区和漏区; 第二晶体管，包括设置成与第一源极区域或第一漏极区域中的至少一部分重叠的第二沟道形成区域，第二源极电极，电连接到第一栅极电极的第二漏极电极，以及 第二栅电极; 以及设置在第一晶体管和第二晶体管之间的绝缘层。 在第二晶体管需要处于截止状态的期间中，至少当向第一源极区域或第一漏极区域提供正电位时，向第二栅电极提供负电位。
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