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27 条记录 (耗时 0.016 秒)

    One-chip first-in first-out memory device having matched write and read operations
    1.
    发明授权
    One-chip first-in first-out memory device having matched write and read operations 失效
    具有匹配的写入和读取操作的单芯片先进先出的存储器件

    公开(公告)号：US5220529A

    公开(公告)日：1993-06-15

    申请号：US747047

    申请日：1991-08-19

    申请人： Kiyoshi Kohiyama ,  Hidenaga Takahashi ,  Yukio Otobe

    发明人： Kiyoshi Kohiyama ,  Hidenaga Takahashi ,  Yukio Otobe

    IPC分类号： G06F5/10 ,  G11C8/04

    CPC分类号： G06F5/10 ,  G11C8/04

    摘要： A write operation is performed by using a sequentially-incremented write address upon a first-in first-out memory device, and a read operation is performed by using a sequentially-incremented read address upon the first-in first-out memory device. The write address is cleared by a write reset signal, and the read address is cleared by a read reset signal. A delay circuit is provided to coincide an effective timing of the write reset signal in the memory cell array with that of the read reset signal in the memory cell array.

    摘要翻译： 通过在先进先出存储器件中使用顺序递增的写入地址来执行写入操作，并且通过在先进先出存储器件中使用顺序递增的读取地址来执行读取操作。 写入地址由写入复位信号清零，读取地址由读取复位信号清零。 提供延迟电路以将存储单元阵列中的写入复位信号的有效定时与存储单元阵列中的读取复位信号的有效定时重合。

    Color image display control apparatus with correction of phase difference in sampling clock
    2.
    发明授权
    Color image display control apparatus with correction of phase difference in sampling clock 失效
    具有采样时钟相位差校正的彩色图像显示控制装置

    公开(公告)号：US5043799A

    公开(公告)日：1991-08-27

    申请号：US369051

    申请日：1989-06-20

    申请人： Kiyoshi Kohiyama ,  Shozo Kobatake ,  Hidenaga Takahashi

    发明人： Kiyoshi Kohiyama ,  Shozo Kobatake ,  Hidenaga Takahashi

    IPC分类号： H04N9/67 ,  H04N9/64 ,  H04N11/04

    CPC分类号： H04N9/64

    摘要： A color image display control apparatus for receiving a composite color picture signal and processing color image data included in the signal. A color picture signal in an analog form included in the composite color picture signal is converted to a digital form by sampling the analog signal at each cycle of a sampling clock, in and analog to digital converter. The digital image data is processed in a digital image processing circuit. Processed digital data is converted to analog data in a digital to analog converter. Information regarding a phase difference between the sampling clock and each horizontal synchronizing signal in the composite color picture signal is obtained. According to the information, a digital image data in a line corresponding to each horizontal synchronizing signal, which was sampled by the sampling clock, is modified so that the influence of the above phase difference on a displayed image of the processed image data is corrected.

    摘要翻译： 一种彩色图像显示控制装置，用于接收复合彩色图像信号并处理包括在该信号中的彩色图像数据。 包含在复合彩色图像信号中的模拟形式的彩色图像信号通过在采样时钟和模数转换器的每个周期采样模拟信号而被转换为数字形式。 数字图像数据在数字图像处理电路中进行处理。 处理的数字数据被转换成数模转换器中的模拟数据。 获得关于合成彩色图像信号中的采样时钟和每个水平同步信号之间的相位差的信息。 根据该信息，修改与由采样时钟采样的每个水平同步信号相对应的行中的数字图像数据，以便校正上述相位差对经处理图像数据的显示图像的影响。

    Method and apparatus for detecting a phase difference between two digital signals
    3.
    发明授权
    Method and apparatus for detecting a phase difference between two digital signals 失效
    用于检测两个数字信号之间的相位差的方法和装置

    公开(公告)号：US4963817A

    公开(公告)日：1990-10-16

    申请号：US372452

    申请日：1989-06-28

    申请人： Kiyoshi Kohiyama ,  Hidenaga Takahashi

    发明人： Kiyoshi Kohiyama ,  Hidenaga Takahashi

    IPC分类号： H03K5/26 ,  G01R25/00 ,  H03D13/00 ,  H03L7/085 ,  H04L7/033

    CPC分类号： G01R25/00

    摘要： In an apparatus for detecting a phase difference between two digital signals including an n stage delay circuit, an n bit register connected to the n stage delay circuit, a signal encoding means connected to the n bit register, and a compensation circuit connected to the encoder, a test signal is applied to the delay circuit first and two different delayed data are obtained by applying a reference signal to the n bit register twice, the delay characteristics of the delay circuit is calculated by using two different data and the period time of the two reference signals, then a signal to be subjected to phase difference detection is applied to the delay circuit to obtain delayed data by applying a reference signal to the n bit register, the delayed data is compensated at the compensating circuit by using the delay characteristics of the delay circuit. Thus, an accurate phase difference between two digital signals is obtained.

    摘要翻译： 在用于检测包括n级延迟电路的两个数字信号，连接到n级延迟电路的n位寄存器，连接到n位寄存器的信号编码装置以及连接到编码器的补偿电路的两个数字信号之间的相位差检测装置中， 首先将测试信号施加到延迟电路，并通过将参考信号施加到n位寄存器两次来获得两个不同的延迟数据，延迟电路的延迟特性通过使用两个不同的数据和 两个参考信号，则通过向n位寄存器施加参考信号，将延迟电路施加到延迟电路上以进行相位差检测的信号以获得延迟的数据，在补偿电路上通过使用延迟特性 延时电路。 因此，获得两个数字信号之间的精确相位差。

    Method and device for decoding moving picture
    4.
    发明授权
    Method and device for decoding moving picture 有权
    解码运动图像的方法和装置

    公开(公告)号：US06658154B2

    公开(公告)日：2003-12-02

    申请号：US09365865

    申请日：1999-08-03

    申请人： Kiyoshi Kohiyama ,  Yukio Otobe ,  Hidenaga Takahashi ,  Koji Yoshitomi

    发明人： Kiyoshi Kohiyama ,  Yukio Otobe ,  Hidenaga Takahashi ,  Koji Yoshitomi

    IPC分类号： G06K946

    CPC分类号： G06T1/60 ,  H04N19/176 ,  H04N19/423 ,  H04N19/61 ,  H04N19/90

    摘要： A memory control part 12 cyclically assigns time slots to buffer memory parts 21 to 25 respectively and in each time slot, controls access between the corresponding buffer memory part and a synchronous RAM 11. A time slot is determined while assuming the worst case where access to the synchronous RAM is the severest. Time slot groups of [(the number of pixels on one horizontal scanning line)/256] in number are generated in an imaginary one horizontal scanning period, where [ ] denotes an integer portion of the number in the parentheses. For a buffer memory 22 whose data volume changes depending on a compression factor, a time slot ending point may be made variable, or a time slot may be generated by interrupt as an exception.

    摘要翻译： 存储器控制部分12分别循环地将时隙分配给缓冲存储器部分21至25，并且在每个时隙中控制对应的缓冲存储器部分和同步RAM 11之间的访问。确定时隙，同时假定访问 同步RAM是最严重的。 数字中的[（一条水平扫描线上的像素数）/ 256]的时隙组在虚拟的一个水平扫描周期中生成，其中[]表示括号中的数字的整数部分。 对于其数据量根据压缩因子而变化的缓冲存储器22，可以使时隙终点可变，或者可以通过中断产生时隙作为例外。

    Information processing apparatus, secure module, information processing method, and computer product
    6.
    发明授权
    Information processing apparatus, secure module, information processing method, and computer product 有权
    信息处理装置，安全模块，信息处理方法和计算机产品

    公开(公告)号：US08984272B2

    公开(公告)日：2015-03-17

    申请号：US13434611

    申请日：2012-03-29

    申请人： Kiyoshi Kohiyama ,  Masakazu Takakusu ,  Kenichi Wakasugi

    发明人： Kiyoshi Kohiyama ,  Masakazu Takakusu ,  Kenichi Wakasugi

    IPC分类号： G06F21/00 ,  G06F21/57 ,  G06F21/54 ,  G06F21/55 ,  G06F21/60 ,  G06F21/62 ,  G06F21/71 ,  G06F21/72 ,  G06F21/86

    CPC分类号： G06F21/57 ,  G06F21/54 ,  G06F21/554 ,  G06F21/602 ,  G06F21/629 ,  G06F21/71 ,  G06F21/72 ,  G06F21/86 ,  G06F2221/033 ,  G06F2221/2101 ,  G06F2221/2107 ,  G06F2221/2143

    摘要： An information processing apparatus securely stores a program group comprising one or more programs and includes a first detector that detects an execution waiting state of a given program among the program group; a secure module that is configured such that information stored therein cannot be referred to by an external device, and when the execution waiting state is detected by the first detector, that encrypts the given program and writes the encrypted given program to a storage area that is different from that of the program group; a second detector that detects an execution request concerning the given program; a decrypter that decrypts the given program encrypted by the secure module and writes the decrypted given program to the storage area, when the execution request concerning the given program is detected by the second detector; and a program executor that executes the given program decrypted by the decrypter.

    摘要翻译： 信息处理装置安全地存储包括一个或多个程序的程序组，并且包括检测程序组中给定程序的执行等待状态的第一检测器; 配置为使得存储在其中的信息不能被外部设备参考的安全模块，并且当第一检测器检测到执行等待状态时，加密给定程序并将加密的给定程序写入存储区域 与程序组不同; 第二检测器，其检测关于所述给定程序的执行请求; 解密器，当由所述第二检测器检测到关于所述给定程序的执行请求时，解密由所述安全模块加密的给定程序并将所述解密的给定程序写入所述存储区域; 以及执行由解密器解密的给定程序的程序执行器。

    Information reproducing apparatus and secure module
    9.
    发明授权
    Information reproducing apparatus and secure module 有权
    信息再现装置和安全模块

    公开(公告)号：US07913094B2

    公开(公告)日：2011-03-22

    申请号：US10305187

    申请日：2002-11-27

    申请人： Kiyoshi Kohiyama ,  Takayuki Hasebe

    发明人： Kiyoshi Kohiyama ,  Takayuki Hasebe

    IPC分类号： G06F11/30 ,  G06F12/14

    CPC分类号： G06F21/33 ,  G06F21/10

    摘要： In an information reproducing apparatus having an open architecture, a secure module stores first information, and has a structure which does not allow access to the first information from outside, and a memory has a structure which can be accessed from outside. A decryption unit loaded in the memory decrypts an encryption applied to the first information by using a predetermined key. A key supply unit implemented in the secure module supplies the predetermined key to the decryption unit. An authentication unit implemented in the secure module supplies second information to the decryption unit, refers to third information returned in response to the second information, and checks for authenticity of the decryption unit. A key-supply stop unit implemented in the secure module stops supply of the predetermined key by the key supply unit when the authentication unit does not authenticate the decryption unit.

    摘要翻译： 在具有开放架构的信息再现装置中，安全模块存储第一信息，并且具有不允许从外部访问第一信息的结构，并且存储器具有可从外部访问的结构。 加载在存储器中的解密单元通过使用预定密钥解密应用于第一信息的加密。 在安全模块中实现的密钥提供单元将预定密钥提供给解密单元。 在安全模块中实现的认证单元将第二信息提供给解密单元，参考响应于第二信息返回的第三信息，并检查解密单元的真实性。 当认证单元不认证解密单元时，在安全模块中实现的按键供应停止单元停止由密钥提供单元提供预定密钥。