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公开(公告)号：US07920699B2
公开(公告)日：2011-04-05
申请号：US12172439
申请日：2008-07-14
申请人： Koichi Fujisaki , Hideyuki Miyake
发明人： Koichi Fujisaki , Hideyuki Miyake
IPC分类号： H04L9/00
CPC分类号： H04L9/302 , G09C1/00 , H04L9/004 , H04L2209/12
摘要： Valid code data and invalid code data are alternately input to a register that fetches data synchronously with a clock signal. A state of a data value input to the register is monitored. Each time when it is determined that the data is stabilized by the valid code data, the register holds the valid code data.
摘要翻译： 有效代码数据和无效代码数据被交替地输入到与时钟信号同步地获取数据的寄存器。 监视输入到寄存器的数据值的状态。 每当确定数据被有效代码数据稳定时，该寄存器保存有效的代码数据。
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公开(公告)号：US20090086962A1
公开(公告)日：2009-04-02
申请号：US12172439
申请日：2008-07-14
申请人： Koichi Fujisaki , Hideyuki Miyake
发明人： Koichi Fujisaki , Hideyuki Miyake
IPC分类号： H04L9/28
CPC分类号： H04L9/302 , G09C1/00 , H04L9/004 , H04L2209/12
摘要： Valid code data and invalid code data are alternately input to a register that fetches data synchronously with a clock signal. A state of a data value input to the register is monitored. Each time when it is determined that the data is stabilized by the valid code data, the register holds the valid code data.
摘要翻译： 有效代码数据和无效代码数据被交替地输入到与时钟信号同步地获取数据的寄存器。 监视输入到寄存器的数据值的状态。 每当确定数据被有效代码数据稳定时，该寄存器保存有效的代码数据。
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公开(公告)号：US08401180B2
公开(公告)日：2013-03-19
申请号：US12053143
申请日：2008-03-21
IPC分类号： H04K1/00
CPC分类号： H04L9/0618 , H04L9/003 , H04L2209/046 , H04L2209/08 , H04L2209/24
摘要： According to an aspect of the present invention, there is provided a non-linear data converter including: first to fourth converters that each performs a respective converting process on an input bit string to output respective output bit string; a generator that generates a random number bit string; and a selector that selects any one of the output bit strings from the first to fourth converters based on the random number bit string. Each of the converting processes is equivalent to performing a first mask process, a non-linear conversion predetermined for an encoding or a decoding and a second mask process.
摘要翻译： 根据本发明的一个方面，提供了一种非线性数据转换器，包括：第一至第四转换器，其对输入的比特串执行相应的转换处理，以输出相应的输出比特串; 产生随机数位串的发生器; 以及选择器，其基于随机数位串来选择来自第一至第四转换器的输出位串中的任何一个。 每个转换处理等效于执行第一掩码处理，为编码或解码预定的非线性转换和第二掩码处理。
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公开(公告)号：US20080292100A1
公开(公告)日：2008-11-27
申请号：US12053143
申请日：2008-03-21
IPC分类号： H04L9/06
CPC分类号： H04L9/0618 , H04L9/003 , H04L2209/046 , H04L2209/08 , H04L2209/24
摘要： According to an aspect of the present invention, there is provided a non-linear data converter including: first to fourth converters that each performs a respective converting process on an input bit string to output respective output bit string; a generator that generates a random number bit string; and a selector that selects any one of the output bit strings from the first to fourth converters based on the random number bit string. Each of the converting processes is equivalent to performing a first mask process, a non-linear conversion predetermined for an encoding or a decoding and a second mask process.
摘要翻译： 根据本发明的一个方面，提供了一种非线性数据转换器，包括：第一至第四转换器，其对输入的比特串执行相应的转换处理，以输出相应的输出比特串; 产生随机数位串的发生器; 以及选择器，其基于随机数位串来选择来自第一至第四转换器的输出位串中的任何一个。 每个转换处理等效于执行第一掩码处理，为编码或解码预定的非线性转换和第二掩码处理。
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公开(公告)号：US08909689B2
公开(公告)日：2014-12-09
申请号：US13361074
申请日：2012-01-30
IPC分类号： G06F7/72
CPC分类号： G06F7/728
摘要： According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.
摘要翻译： 根据一个实施例，第一移位量计算单元从蒙哥马利乘积结果z的计算的中间结果的较低有效位向更高有效位对连续零的数进行计数，并计算第一移位量。 第二移位量计算单元将来自冗余二进制表示的整数x的较低有效位朝向更高有效位的连续零的数目计数，并计算第二移位量。 加法/减法单元相对于已被移位了第一移位量的中间结果，整数p和已被位移第二移位的整数y加/减来计算中间结果 量。 当第一移位量的和等于整数p的位数时，输出单元输出作为蒙哥马利乘数结果z的中间结果。
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公开(公告)号：US08578172B2
公开(公告)日：2013-11-05
申请号：US13050332
申请日：2011-03-17
申请人： Koichi Fujisaki
发明人： Koichi Fujisaki
IPC分类号： H04L9/32
CPC分类号： H04L9/0816 , H04L9/3242
摘要： One embodiment is an information processing device for obtaining an HMAC, including a padding circuit for generating first key data by adding a first constant with respect to secret key data, setting the secret key data as second key data when the secret key length is equal to the block length, generating third key data by adding the first constant with respect to a first digest value; a hash calculation circuit for obtaining the first digest value; and a control unit for managing a processing state for calculating the HMAC, wherein the hash calculation circuit outputs a first midway progress value when interrupting a calculation process of the first digest value, and resumes the calculation process of the first digest using the first midway progress value when a signal indicating resuming instruction of the calculation process of the first digest value is input to the control unit.
摘要翻译： 一个实施例是一种用于获得HMAC的信息处理设备，包括：填充电路，用于通过相对于秘密密钥数据添加第一常数来生成第一密钥数据;将秘密密钥数据设置为第二密钥数据，当秘密密钥长度等于 块长度，通过相对于第一摘要值添加第一常数来产生第三密钥数据; 用于获得第一摘要值的散列计算电路; 以及控制单元，用于管理用于计算HMAC的处理状态，其中，当中断第一摘要值的计算处理时，散列计算电路输出第一中途进度值，并且使用第一中途进度来恢复第一摘要的计算处理 当指示第一摘要值的计算处理的恢复指令的信号被输入到控制单元时的值。
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公开(公告)号：US20120246501A1
公开(公告)日：2012-09-27
申请号：US13345824
申请日：2012-01-09
申请人： Hiroyoshi Haruki , Koichi Fujisaki , Satoshi Shirai , Masaya Tarui , Akihiro Shibata , Tetsuro Kimura , Tatsunori Kanai , Haruhiko Toyama
发明人： Hiroyoshi Haruki , Koichi Fujisaki , Satoshi Shirai , Masaya Tarui , Akihiro Shibata , Tetsuro Kimura , Tatsunori Kanai , Haruhiko Toyama
IPC分类号： G06F1/32
CPC分类号： G06F9/4893 , G06F1/3228 , G06F1/324 , G06F1/3243 , G06F1/3287 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/24 , Y02D50/20
摘要： According to one embodiment, a controller includes a state detecting unit, a calculating unit, and a determining unit. The state detecting unit detects an idle state in which indicates there are no process that can execute on a processing device capable of performing one or more processes. The calculating unit calculates a resuming time, which indicates a time length until the next process starts, when the state detecting unit detects the idle state. The determining unit determines an operation mode of the processing device on the basis of the resuming time calculated by the calculating unit.
摘要翻译： 根据一个实施例，控制器包括状态检测单元，计算单元和确定单元。 状态检测单元检测空闲状态，其中表示不能在能够执行一个或多个处理的处理设备上执行的处理。 当状态检测单元检测到空闲状态时，计算单元计算恢复时间，其指示直到下一个处理开始的时间长度。 确定单元基于由计算单元计算的恢复时间来确定处理装置的操作模式。
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8.发明授权Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device 有权随机数测试电路，随机数生成电路，半导体集成电路，IC卡和信息终端设备公开(公告)号：US07653855B2
公开(公告)日：2010-01-26
申请号：US11875360
申请日：2007-10-19
CPC分类号： G06F7/58 , G01R31/3181
摘要： A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.
摘要翻译： 随机数测试电路包括：计数单元，用于对随机数序列中的特定值比特的重复次数进行计数，串联发生的重复;检测单元，用于检测与随机数中的比特种类对应的多个数字 数字序列，以及基于该数字确定随机数序列是否正常的确定单元。
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公开(公告)号：US20070005895A1
公开(公告)日：2007-01-04
申请号：US11477398
申请日：2006-06-30
申请人： Koichi Fujisaki , Hideo Shimizu
发明人： Koichi Fujisaki , Hideo Shimizu
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F12/0886 , G06F12/14 , G06F2212/601
摘要： A cache controller is connected to a processor and a main memory. The cache controller is also connected to a cache memory that can read and write at a speed higher than the main memory. The cache memory is provided with a plurality of cache lines that include a tag area storing an address on the main memory, a capacity area storing a capacity value of a cache block, and a cache block. When a read request is executed from the processor to the main memory, the cache controller checks whether the requested data is present in the cache memory or not. A cache capacity determination unit determines a capacity value for the cache block and supplies to a capacity area.
摘要翻译： 缓存控制器连接到处理器和主存储器。 高速缓存控制器还连接到可以以比主存储器高的速度读写的高速缓冲存储器。 高速缓冲存储器设置有多条高速缓存线，其包括存储主存储器上的地址的标签区域，存储高速缓存块的容量值的容量区域和高速缓存块。 当从处理器向主存储器执行读请求时，高速缓存控制器检查所请求的数据是否存在于高速缓冲存储器中。 高速缓存容量确定单元确定高速缓存块的容量值并提供给容量区。
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10.发明授权Memory modules with magnetoresistive elements and method of reading data from row or column directions 失效具有磁阻元件的存储器模块和从行或列方向读取数据的方法公开(公告)号：US07123539B2
公开(公告)日：2006-10-17
申请号：US11180558
申请日：2005-07-14
IPC分类号： G11C8/00
CPC分类号： G06F12/0207 , G11C8/10
摘要： A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction. In this manner, data is read from a magnetoresistive memory module in both row and column directions.
摘要翻译： 存储单元模块包括由M列×N行的存储器单元形成的存储单元阵列。 每个存储单元包括具有半导体元件的磁阻元件或磁阻元件。 存储器模块包括通过列方向访问存储单元阵列的第一存取装置和通过行方向访问存储单元阵列的第二存取装置。 以这种方式，在行和列方向上从磁阻存储器模块读取数据。
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