公开(公告)号：US09224759B2

公开(公告)日：2015-12-29

申请号：US13305320

申请日：2011-11-28

申请人： Koichi Nagasawa ,  Masaya Tamaki ,  Shuji Hayashi ,  Masaaki Kabe ,  Yoko Fukunaga

发明人： Koichi Nagasawa ,  Masaya Tamaki ,  Shuji Hayashi ,  Masaaki Kabe ,  Yoko Fukunaga

IPC分类号： G02F1/1343 ,  H01L27/12

CPC分类号： G02F1/134336 ,  G02F1/13306 ,  G02F1/133707 ,  G02F1/13452 ,  G02F2001/133742 ,  G02F2001/134345 ,  H01L27/124 ,  H01L27/1248

摘要： A pixel array substrate structure includes: first and second planarizing films sequentially stacked on a substrate where a circuit unit is formed; and a relay wire formed between the first and second planarizing films, in which the relay wire electrically connects a first contact portion formed on the first planarizing film and connected to the circuit unit with a second contact portion formed at a position different from the first contact portion when seen from above, on the second planarizing film.

摘要翻译： 像素阵列基板结构包括：顺序堆叠在形成电路单元的基板上的第一和第二平坦化膜; 以及形成在所述第一和第二平坦化膜之间的中继线，其中所述继电器线将形成在所述第一平坦化膜上的第一接触部分电连接到所述电路单元，所述第二接触部形成在与所述第一接触部不同的位置处的第二接触部 在第二平面化膜上从上方观察。

公开(公告)号：US08830436B2

公开(公告)日：2014-09-09

申请号：US13305316

申请日：2011-11-28

申请人： Masaya Tamaki ,  Koichi Nagasawa ,  Shuji Hayashi ,  Masaaki Kabe ,  Yoko Fukunaga

发明人： Masaya Tamaki ,  Koichi Nagasawa ,  Shuji Hayashi ,  Masaaki Kabe ,  Yoko Fukunaga

IPC分类号： G02F1/1343 ,  G09G3/36 ,  G02F1/1362 ,  G09G3/20 ,  G02F1/1333

CPC分类号： G02F1/13624 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/133357 ,  G02F2001/134345 ,  G02F2001/13629 ,  G02F2203/30 ,  G09G3/207 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/0443 ,  G09G2300/0857

摘要： A pixel structure includes: a first planarizing film and a second planarizing film laminated in order on a substrate on which a circuit section is formed; and metallic wiring for electrically connecting two electrodes disposed on the second planarizing film to each other so as to be separated from each other, the metallic wiring being formed between the first planarizing film and the second planarizing film.

摘要翻译： 像素结构包括：第一平面化膜和第二平面化膜依次层叠在其上形成有电路部分的基板上; 以及用于将设置在所述第二平坦化膜上的两个电极彼此分离地彼此分离的金属布线，所述金属布线形成在所述第一平坦化膜和所述第二平坦化膜之间。

公开(公告)号：US20120162594A1

公开(公告)日：2012-06-28

申请号：US13305316

申请日：2011-11-28

申请人： Masaya Tamaki ,  Koichi Nagasawa ,  Shuji Hayashi ,  Masaaki Kabe ,  Yoko Fukunaga

发明人： Masaya Tamaki ,  Koichi Nagasawa ,  Shuji Hayashi ,  Masaaki Kabe ,  Yoko Fukunaga

IPC分类号： G02F1/1343

CPC分类号： G02F1/13624 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/133357 ,  G02F2001/134345 ,  G02F2001/13629 ,  G02F2203/30 ,  G09G3/207 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/0443 ,  G09G2300/0857

摘要： A pixel structure includes: a first planarizing film and a second planarizing film laminated in order on a substrate on which a circuit section is formed; and metallic wiring for electrically connecting two electrodes disposed on the second planarizing film to each other so as to be separated from each other, the metallic wiring being formed between the first planarizing film and the second planarizing film.

摘要翻译： 像素结构包括：第一平面化膜和第二平面化膜依次层叠在其上形成有电路部分的基板上; 以及用于将设置在所述第二平坦化膜上的两个电极彼此分离地彼此分离的金属布线，所述金属布线形成在所述第一平坦化膜和所述第二平坦化膜之间。

公开(公告)号：US20120154736A1

公开(公告)日：2012-06-21

申请号：US13305320

申请日：2011-11-28

申请人： Koichi Nagasawa ,  Masaya Tamaki ,  Shuji Hayashi ,  Masaaki Kabe ,  Yoko Fukunaga

发明人： Koichi Nagasawa ,  Masaya Tamaki ,  Shuji Hayashi ,  Masaaki Kabe ,  Yoko Fukunaga

IPC分类号： G02F1/1333

CPC分类号： G02F1/134336 ,  G02F1/13306 ,  G02F1/133707 ,  G02F1/13452 ,  G02F2001/133742 ,  G02F2001/134345 ,  H01L27/124 ,  H01L27/1248

摘要： A pixel array substrate structure includes: first and second planarizing films sequentially stacked on a substrate where a circuit unit is formed; and a relay wire formed between the first and second planarizing films, in which the relay wire electrically connects a first contact portion formed on the first planarizing film and connected to the circuit unit with a second contact portion formed at a position different from the first contact portion when seen from above, on the second planarizing film.

摘要翻译： 像素阵列基板结构包括：顺序堆叠在形成电路单元的基板上的第一和第二平坦化膜; 以及形成在所述第一和第二平坦化膜之间的中继线，其中所述继电器线将形成在所述第一平坦化膜上的第一接触部分电连接到所述电路单元，所述第二接触部形成在与所述第一接触部不同的位置处的第二接触部 在第二平面化膜上从上方观察。

公开(公告)号：US08355108B2

公开(公告)日：2013-01-15

申请号：US12510402

申请日：2009-07-28

申请人： Takeo Koito ,  Koichi Nagasawa ,  Shuji Hayashi ,  Hidehiro Kosaka

发明人： Takeo Koito ,  Koichi Nagasawa ,  Shuji Hayashi ,  Hidehiro Kosaka

IPC分类号： G02F1/1339

CPC分类号： G02F1/13338 ,  G02F1/13394 ,  G02F2001/13396

摘要： A liquid-crystal display device includes a first substrate; a second substrate formed so as to oppose the first substrate; a liquid-crystal layer with a predetermined thickness, the liquid-crystal layer being formed between the first substrate and the second substrate; a planarization film for planarizing the surface of the liquid-crystal layer, the planarization film being formed on the surface of at least one of the first substrate and the second substrate, the surface facing the liquid-crystal layer; and projecting parts that are integrally formed with the planarization film.

摘要翻译： 液晶显示装置包括：第一基板; 形成为与第一基板相对的第二基板; 具有预定厚度的液晶层，所述液晶层形成在所述第一基板和所述第二基板之间; 用于平坦化液晶层表面的平坦化膜，所述平坦化膜形成在所述第一基板和所述第二基板中的至少一个的表面上，所述表面面向所述液晶层; 以及与平坦化膜一体形成的突出部。

公开(公告)号：US20100033668A1

公开(公告)日：2010-02-11

申请号：US12510402

申请日：2009-07-28

申请人： Takeo Koito ,  Koichi Nagasawa ,  Shuji Hayashi ,  Hidehiro Kosaka

发明人： Takeo Koito ,  Koichi Nagasawa ,  Shuji Hayashi ,  Hidehiro Kosaka

IPC分类号： G02F1/1339 ,  G02F1/13

CPC分类号： G02F1/13338 ,  G02F1/13394 ,  G02F2001/13396

摘要： A liquid-crystal display device includes a first substrate; a second substrate formed so as to oppose the first substrate; a liquid-crystal layer with a predetermined thickness, the liquid-crystal layer being formed between the first substrate and the second substrate; a planarization film for planarizing the surface of the liquid-crystal layer, the planarization film being formed on the surface of at least one of the first substrate and the second substrate, the surface facing the liquid-crystal layer; and projecting parts that are integrally formed with the planarization film.

摘要翻译： 液晶显示装置包括：第一基板; 形成为与第一基板相对的第二基板; 具有预定厚度的液晶层，所述液晶层形成在所述第一基板和所述第二基板之间; 平坦化膜，用于使液晶层的表面平坦化，所述平坦化膜形成在所述第一基板和所述第二基板中的至少一个的表面上，所述表面面向所述液晶层; 以及与平坦化膜一体形成的突出部。

公开(公告)号：US07838402B2

公开(公告)日：2010-11-23

申请号：US12275448

申请日：2008-11-21

申请人： Koichi Nagasawa ,  Takashi Yamaguchi ,  Nobutaka Ozaki ,  Yasuhiro Kanaya ,  Hirohisa Takeda ,  Yasuo Mikami ,  Yoshifumi Mutoh

发明人： Koichi Nagasawa ,  Takashi Yamaguchi ,  Nobutaka Ozaki ,  Yasuhiro Kanaya ,  Hirohisa Takeda ,  Yasuo Mikami ,  Yoshifumi Mutoh

IPC分类号： H01L21/26 ,  H01L21/42

CPC分类号： H01L29/78633 ,  G02F1/133555 ,  G02F1/13394 ,  G02F1/136227 ,  H01L27/1248

摘要： A method of manufacturing an electronic apparatus having a resist pattern provided over a substrate provided with a thin film transistor, the method includes the steps of forming by application a resist film over the substrate in the state of covering the thin film transistor, forming a resist pattern by subjecting the resist film to exposure to light and a developing treatment, and irradiating the resist pattern with at least one of ultraviolet light and visible light in a dry atmosphere in the condition where a channel part of the thin film transistor is prevented from being irradiated with light having a wavelength of shorter than 260 nm, wherein a step of heat curing the resist pattern is conducted after the irradiation with at least one of ultraviolet light and visible light.

摘要翻译： 一种制造具有设置在设置有薄膜晶体管的基板上的抗蚀剂图案的电子设备的方法，该方法包括以下步骤：在覆盖薄膜晶体管的状态下在基板上施加抗蚀剂膜，形成抗蚀剂 通过使抗蚀剂膜曝光并进行显影处理，并且在防止薄膜晶体管的沟道部分被阻止的条件下，在干燥气氛中用紫外光和可见光中的至少一种照射抗蚀剂图案 用波长短于260nm的光照射，其中在用紫外光和可见光中的至少一种照射之后进行热固化抗蚀图案的步骤。

公开(公告)号：US07187039B2

公开(公告)日：2007-03-06

申请号：US11101446

申请日：2005-04-08

申请人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

发明人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

IPC分类号： H01L29/76

CPC分类号： H01L23/562 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/585 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

公开(公告)号：US20050040537A1

公开(公告)日：2005-02-24

申请号：US10951939

申请日：2004-09-29

申请人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

发明人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

IPC分类号： H01L21/76 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/00 ,  H01L27/108 ,  H01L29/40

CPC分类号： H01L23/562 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/585 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

公开(公告)号：US06261883B1

公开(公告)日：2001-07-17

申请号：US09050416

申请日：1998-03-31

申请人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

发明人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

IPC分类号： H01L21336

CPC分类号： H01L23/562 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/585 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

摘要翻译： 在覆盖形成在半导体衬底的主表面上的MISFETQ1的层间绝缘膜上形成互连，而虚设互连设置在与这种相互连接的区域中。 虚拟互连也布置在划线区域中。 在接合焊盘和标记的周边不形成虚拟互连。 此外，设置MISFET的栅电极和由相同层形成的虚拟栅极互连。 此外，虚设区域设置在浅沟槽元件隔离区域中。 在这样的虚设部件设置之后，通过CMP方法将绝缘膜平坦化。