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    Memory module
    3.
    发明授权
    Memory module 失效
    内存模块

    公开(公告)号：US06515922B1

    公开(公告)日：2003-02-04

    申请号：US09621693

    申请日：2000-07-21

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： G11C700

    CPC分类号： G11C29/40

    摘要： A memory module is provided with switch groups (SD0a to SD7a) in corresponding relation to data lines (DQ0 to DQ63) connected to memory devices (MD0 to MD7). The switch groups (SD0a to SD7a) connect all of the data lines (DQ0 to DQ63) to a portion external to the memory module (MMa) in a memory operation, and connect all of the data lines (DQ0 to DQ63) to inputs of an exclusive NOR circuit (EXa) after common 1-bit data is written into the memory devices (MD0 to MD7) in a testing operation. A malfunction of the memory devices (MD0 to MD7) is detected using an output signal (TMSa) from the exclusive NOR circuit (EXa). The memory module is accomplished which allows an inexpensive tester to conduct an electrical assembly check and a simple data write and read operation test upon the memory devices, which includes a small number of I/O pins for the check and test, and which does not deteriorate data input/output characteristics of the memory devices.

    摘要翻译： 存储器模块具有与连接到存储器件（MD0至MD7）的数据线（DQ0至DQ63）对应关系的开关组（SD0a至SD7a）。 开关组（SD0a〜SD7a）在存储器动作中将所有数据线（DQ0〜DQ63）连接到存储器模块外部的一部分（MMa），并将所有数据线（DQ0〜DQ63）连接到 在测试操作中，将公共1位数据写入存储器件（MD0至MD7）之后的异或电路（EXa）。 使用来自异或电路（EXa）的输出信号（TMSa）来检测存储器件（MD0至MD7）的故障。 完成了内存模块，允许廉价的测试人员对存储设备进行电气组装检查和简单的数据写入和读取操作测试，存储器件包括少量用于检查和测试的I / O引脚，不存在 恶化了存储器件的数据输入/输出特性。

    Fast memory device allowing suppression of peak value of operational current
    5.
    发明授权
    Fast memory device allowing suppression of peak value of operational current 失效
    快速存储器件允许抑制工作电流的峰值

    公开(公告)号：US5726943A

    公开(公告)日：1998-03-10

    申请号：US583810

    申请日：1996-01-05

    申请人： Tadato Yamagata ,  Kazutami Arimoto

    发明人： Tadato Yamagata ,  Kazutami Arimoto

    IPC分类号： G11C7/06 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C8/00

    CPC分类号： G11C11/4091 ,  G11C11/406 ,  G11C7/065

    摘要： A memory cell array of a dynamic semiconductor memory device is divided into a plurality of memory cell blocks. A block selecting circuit selects and refreshes larger number of memory cell blocks in refreshing mode than the number of those selected during normal mode. Sense amplifiers in the memory cell blocks selected by the block selecting circuit are selectively driven with smaller driving force in refreshing mode than that in normal mode. More preferably the driving force is changed during the amplifying operation so as to achieve both the high sensitivity and the suppression of the peak value of the operational current.

    摘要翻译： 动态半导体存储器件的存储单元阵列被分成多个存储单元块。 块选择电路在更新模式下选择和刷新大量的在正常模式下选择的存储单元块的数量。 通过块选择电路选择的存储单元块中的感测放大器在刷新模式下以比正常模式更小的驱动力被选择性地驱动。 更优选地，在放大操作期间驱动力被改变，以便实现操作电流的峰值的高灵敏度和抑制。

    Test circuit of semiconductor memory device
    6.
    发明授权
    Test circuit of semiconductor memory device 失效
    半导体存储器件的测试电路

    公开(公告)号：US5228000A

    公开(公告)日：1993-07-13

    申请号：US733028

    申请日：1991-07-22

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： G11C29/28 ,  G11C29/32

    CPC分类号： G11C29/28 ,  G11C29/32

    摘要： In a test mode, bit information of the same logic is written into a corresponding memory cell of each of subarray 5a-5d. Bit information written in respective memory cells is simultaneously read and supplied to exclusive-OR gates 12a-12d. Each of exclusive-OR gates logics of read bit information and an expected value data supplied as an input to an external input pin D.sub.IN to supply the test determination result as an output. The outputs of respective exclusive-OR gates 12a-12d are serially supplied, through transistors 18a-18d which are sequentially and selectively turned on by a shift register 15, to an external output pin D.sub.OUT.

    摘要翻译： 在测试模式中，将相同逻辑的位信息写入子阵列5a-5d的相应存储单元。 写入各个存储单元的位信息被同时读取并提供给异或门12a-12d。 读取位信息的异或门逻辑和作为输入提供给外部输入引脚DIN的期望值数据，以将测试确定结果作为输出。 通过由移位寄存器15依次选择性地导通的晶体管18a-18d向外部输出引脚DOUT串联提供各异或门12a-12d的输出。

    Content addressable semiconductor memory device and operating method therefor
    7.
    发明授权
    Content addressable semiconductor memory device and operating method therefor 失效
    内容可寻址半导体存储器件及其操作方法

    公开(公告)号：US5126968A

    公开(公告)日：1992-06-30

    申请号：US605707

    申请日：1990-10-30

    申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

    发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

    IPC分类号： G11C15/04

    CPC分类号： G11C15/043 ,  G11C15/04

    摘要： A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of "1" is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data "1", writing of the data "1" onto the bit lines and the inversion bit lines is performed. Then, the data of "0" is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data "0", writing of the data "0" onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.

    摘要翻译： 半导体存储器件包括多个或多个单元。 在刷新操作中，将数据“1”应用于所有位线和反转位线。 在存储数据“1”的CAM单元中，执行数据“1”到位线和反转位线的写入。 然后，将数据“0”应用于所有的位线和反转位线。 在存储数据“0”的CAM单元中，执行数据“0”到位线和反转位线的写入。 在部分写入操作中，在执行写入的CAM单元中，第一控制节点被激活，从而使得可以写入CAM单元。 在其余的CAM单元中，第一控制节点被去激活，从而不可能写入CAM单元。

    Semiconductor integrated circuit device having hierarchical power source arrangement
    8.
    发明授权
    Semiconductor integrated circuit device having hierarchical power source arrangement 失效

    公开(公告)号：US06525984B2

    公开(公告)日：2003-02-25

    申请号：US10047104

    申请日：2002-01-17

    申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

    发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

    IPC分类号： G11C700

    CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

    摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

    Multi-bank semiconductor memory device suitable for integration with logic
    9.
    发明授权
    Multi-bank semiconductor memory device suitable for integration with logic 失效
    适合与逻辑集成的多存储半导体存储器件

    公开(公告)号：US06310815B1

    公开(公告)日：2001-10-30

    申请号：US09131346

    申请日：1998-08-07

    申请人： Tadato Yamagata ,  Akira Yamazaki ,  Shigeki Tomishima ,  Yoshio Yukinari ,  Makoto Hatakenaka ,  Atsushi Miyanishi

    发明人： Tadato Yamagata ,  Akira Yamazaki ,  Shigeki Tomishima ,  Yoshio Yukinari ,  Makoto Hatakenaka ,  Atsushi Miyanishi

    IPC分类号： G11C800

    CPC分类号： G11C5/14 ,  G11C8/12

    摘要： Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these subbanks, and internal read/write data buses are arranged in a region different from the region where the bank control circuits are arranged. Since there is no crossing of the bank control circuits and the internal read/write data buses, the bank control circuits can be efficiently arranged to reduce the layout area. Accordingly, a semiconductor integrated circuit device including multi-bank memories which operates stably at high speed can be provided without increase of an area occupied by a chip.

    摘要翻译： 子行排列在具有矩形形状的DRAM宏的四个区域中，组控制电路布置在这些子行之间的规定区域中，并且内部读/写数据总线布置在与存储体控制电路的区域不同的区域中 安排。 由于银行控制电路和内部读/写数据总线没有交叉，因此可以有效地布置存储体控制电路以减少布局面积。 因此，可以在不增加芯片占有面积的情况下提供包括以高速稳定运行的多存储体存储器的半导体集成电路器件。

    Method of manufacturing semiconductor device
    10.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06214664B1

    公开(公告)日：2001-04-10

    申请号：US09443016

    申请日：1999-11-18

    申请人： Hiroshi Kimura ,  Tadashi Nishimura ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tadato Yamagata ,  Kazuyasu Fujishima

    发明人： Hiroshi Kimura ,  Tadashi Nishimura ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tadato Yamagata ,  Kazuyasu Fujishima

    IPC分类号： H01L218242

    CPC分类号： H01L27/10852

    摘要： In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.

    摘要翻译： 在半导体器件及其制造方法中，隔离绝缘膜设置在与第二杂质区相邻的端部处，并且沟槽延伸到半导体衬底。 这消除了隔离和绝缘膜末端存在的晶体缺陷，从而防止在该部分处的电流从存储节点泄漏。 因此，在与杂质区相邻的隔离氧化膜的边缘部分处设置沟槽消除了该区域的晶体缺陷，从而消除了电流泄漏的可能性。