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公开(公告)号:US20090267068A1
公开(公告)日:2009-10-29
申请号:US12429486
申请日:2009-04-24
申请人: Koji DAIRIKI , Hidekazu MIYAIRI , Toshiyuki ISA , Akiharu MIYANAGA , Takuya HIROHASHI , Shunpei YAMAZAKI , Takeyoshi WATABE
发明人: Koji DAIRIKI , Hidekazu MIYAIRI , Toshiyuki ISA , Akiharu MIYANAGA , Takuya HIROHASHI , Shunpei YAMAZAKI , Takeyoshi WATABE
IPC分类号: H01L29/786
CPC分类号: H01L27/127 , H01J37/32091 , H01L27/1214 , H01L27/1218 , H01L27/1288 , H01L29/04 , H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/78696
摘要: The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which forms a source region and a drain region; and a buffer layer formed from an amorphous semiconductor, which is located between the semiconductor layer and the impurity semiconductor layer. The thin film transistor includes the crystal region which includes minute crystal grains and inverted conical or inverted pyramidal grain each of which grows approximately radially from a position away from an interface between the gate insulating layer and the semiconductor layer toward a direction in which the semiconductor layer is deposited in a region which does not reach the impurity semiconductor layer.
摘要翻译: 薄膜晶体管包括覆盖栅电极的栅极绝缘层,在具有绝缘表面的基板上; 形成在非晶结构中包含多个晶体区域的沟道形成区域的半导体层; 赋予形成源极区域和漏极区域的一种导电型的杂质半导体层; 以及由位于半导体层和杂质半导体层之间的非晶半导体形成的缓冲层。 薄膜晶体管包括晶体区域,其包括微小晶粒和倒圆锥形或倒棱锥晶粒,其每个从远离栅极绝缘层和半导体层之间的界面的位置朝向半导体层的方向大致径向地生长 沉积在不到达杂质半导体层的区域中。
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公开(公告)号:US20100127261A1
公开(公告)日:2010-05-27
申请号:US12467005
申请日:2009-05-15
IPC分类号: H01L29/786
CPC分类号: H01L29/78696 , H01L27/1288 , H01L29/66765 , H01L29/78669
摘要: The thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode, an amorphous semiconductor layer over the gate insulating layer, a semiconductor layer including an impurity element imparting one conductivity type over the amorphous semiconductor layer. The amorphous semiconductor layer comprises an NH radical. Defects of the amorphous semiconductor layer are reduced by cross-linking dangling bonds with the NH radical in the amorphous semiconductor layer.
摘要翻译: 薄膜晶体管包括在具有绝缘表面的衬底上,覆盖栅电极的栅极绝缘层,栅极绝缘层上的非晶半导体层,包括在非晶半导体层上赋予一种导电类型的杂质元素的半导体层。 非晶半导体层包含NH自由基。 通过与非晶半导体层中的NH自由基交联悬挂键来减少非晶半导体层的缺陷。
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公开(公告)号:US20090321737A1
公开(公告)日:2009-12-31
申请号:US12490447
申请日:2009-06-24
申请人: Toshiyuki ISA , Yasuhiro JINBO , Sachiaki TEZUKA , Koji DAIRIKI , Hidekazu MIYAIRI , Shunpei YAMAZAKI , Takuya HIROHASHI
发明人: Toshiyuki ISA , Yasuhiro JINBO , Sachiaki TEZUKA , Koji DAIRIKI , Hidekazu MIYAIRI , Shunpei YAMAZAKI , Takuya HIROHASHI
IPC分类号: H01L29/04
CPC分类号: H01L27/1288 , H01L27/1214 , H01L29/04 , H01L29/66765 , H01L29/78696
摘要: A thin film transistor includes, as a buffer layer, a semiconductor layer which contains nitrogen and includes crystal regions in an amorphous structure between a gate insulating layer and source and drain regions, at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.
摘要翻译: 至少在源区和漏区侧,薄膜晶体管包括作为缓冲层的半导体层,该半导体层含有氮并且包括在栅极绝缘层和源极和漏极区之间的非晶结构中的晶体区域。 与在沟道形成区域中包含非晶半导体的薄膜晶体管相比,可以提高薄膜晶体管的导通电流。 此外,与在沟道形成区域中包含微晶半导体的薄膜晶体管相比,可以减小薄膜晶体管的截止电流。
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公开(公告)号:US20090321743A1
公开(公告)日:2009-12-31
申请号:US12490458
申请日:2009-06-24
申请人: Toshiyuki ISA , Yasuhiro JINBO , Sachiaki TEZUKA , Koji DAIRIKI , Hidekazu MIYAIRI , Shunpei YAMAZAKI
发明人: Toshiyuki ISA , Yasuhiro JINBO , Sachiaki TEZUKA , Koji DAIRIKI , Hidekazu MIYAIRI , Shunpei YAMAZAKI
IPC分类号: H01L29/786
CPC分类号: H01L27/1288 , H01L27/1214 , H01L29/04 , H01L29/66765 , H01L29/78696
摘要: A thin film transistor includes, as a buffer layer, an amorphous semiconductor layer having nitrogen or an NH group between a gate insulating layer and source and drain regions and at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.
摘要翻译: 薄膜晶体管包括作为缓冲层的至少在源极和漏极区域上具有氮或NH基的非晶半导体层,栅极绝缘层与源极和漏极区之间。 与在沟道形成区域中包含非晶半导体的薄膜晶体管相比,可以提高薄膜晶体管的导通电流。 此外,与在沟道形成区域中包含微晶半导体的薄膜晶体管相比,可以减小薄膜晶体管的截止电流。
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公开(公告)号:US20110318875A1
公开(公告)日:2011-12-29
申请号:US13230905
申请日:2011-09-13
IPC分类号: H01L21/34
CPC分类号: H01L29/66772 , H01L29/6675 , H01L29/78618 , H01L29/7869
摘要: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
摘要翻译: 一个实施例是包括交错(顶栅结构)薄膜晶体管,其中使用含有In,Ga和Zn的氧化物半导体膜作为半导体层,并且缓冲层设置在半导体层与源极和漏极之间 层。 有意地在源极和漏极电极层与半导体层之间提供具有比半导体层高的载流子浓度的缓冲层,从而形成欧姆接触。
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公开(公告)号:US20100032667A1
公开(公告)日:2010-02-11
申请号:US12535714
申请日:2009-08-05
IPC分类号: H01L29/786 , H01L21/336
CPC分类号: H01L29/7869 , H01L29/78618
摘要: One of the objects of the present invention is to provide a thin film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the contact resistance between the oxide semiconductor layer and a source and drain electrodes is reduced, and to provide a method for manufacturing the thin film transistor. An ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the IGZO semiconductor layer and the source and drain electrode layers.
摘要翻译: 本发明的目的之一是提供一种使用含有铟(In),镓(Ga)和锌(Zn))的氧化物半导体膜的薄膜晶体管,其中氧化物半导体层和源极之间的接触电阻 并且减少了漏电极,并且提供了制造薄膜晶体管的方法。 通过有意地提供具有比IGZO半导体层和源极和漏极电极层之间的IGZO半导体层更高的载流子浓度的缓冲层来形成欧姆接触。
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公开(公告)号:US20100025676A1
公开(公告)日:2010-02-04
申请号:US12511252
申请日:2009-07-29
IPC分类号: H01L29/786 , H01L21/336
CPC分类号: H01L29/7869 , H01L27/1225 , H01L29/42384 , H01L29/66969 , H01L29/78618
摘要: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
摘要翻译: 提供一种包括具有优异特性和高可靠性的薄膜晶体管的半导体器件以及不改变半导体器件的制造方法。 总结在于包括反向交错(底栅结构)薄膜晶体管,其中包含In,Ga和Zn的氧化物半导体膜用于半导体层,并且在半导体层和源之间提供缓冲层, 漏电极层。 通过有意地提供包含In,Ga和Zn的缓冲层并且具有比半导体层和源极和漏极电极层之间的半导体层更高的载流子浓度来形成欧姆接触。
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公开(公告)号:US20120273780A1
公开(公告)日:2012-11-01
申请号:US13547377
申请日:2012-07-12
IPC分类号: H01L29/12
CPC分类号: H01L29/78618 , G02F1/133345 , G02F1/133528 , G02F1/134336 , G02F1/13439 , G02F1/136286 , G02F1/1368 , G02F1/167 , G02F2201/123 , G09G3/3674 , G09G2310/0286 , H01L27/1225 , H01L27/3262 , H01L29/247 , H01L29/66969 , H01L29/78648 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
摘要翻译: 一个实施例是包括反向交错(底栅结构)薄膜晶体管,其中使用含有In,Ga和Zn的氧化物半导体膜作为半导体层,并且缓冲层设置在半导体层与源极和漏极之间 电极层。 有意地在源极和漏极电极层与半导体层之间提供具有比半导体层高的载流子浓度的缓冲层,从而形成欧姆接触。
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公开(公告)号:US20100032665A1
公开(公告)日:2010-02-11
申请号:US12535711
申请日:2009-08-05
IPC分类号: H01L29/786 , H01L21/34
CPC分类号: H01L29/66772 , H01L29/6675 , H01L29/78618 , H01L29/7869
摘要: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
摘要翻译: 一个实施例是包括交错(顶栅结构)薄膜晶体管,其中使用含有In,Ga和Zn的氧化物半导体膜作为半导体层,并且缓冲层设置在半导体层与源极和漏极之间 层。 有意地在源极和漏极电极层与半导体层之间提供具有比半导体层高的载流子浓度的缓冲层,从而形成欧姆接触。
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公开(公告)号:US20100025679A1
公开(公告)日:2010-02-04
申请号:US12511291
申请日:2009-07-29
IPC分类号: H01L33/00
CPC分类号: H01L29/78618 , G02F1/133345 , G02F1/133528 , G02F1/134336 , G02F1/13439 , G02F1/136286 , G02F1/1368 , G02F1/167 , G02F2201/123 , G09G3/3674 , G09G2310/0286 , H01L27/1225 , H01L27/3262 , H01L29/247 , H01L29/66969 , H01L29/78648 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
摘要翻译: 一个实施例是包括反向交错(底栅结构)薄膜晶体管,其中使用含有In,Ga和Zn的氧化物半导体膜作为半导体层,并且缓冲层设置在半导体层与源极和漏极 电极层。 有意地在源极和漏极电极层与半导体层之间提供具有比半导体层高的载流子浓度的缓冲层,从而形成欧姆接触。
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