公开(公告)号：US20170018625A1

公开(公告)日：2017-01-19

申请号：US15193571

申请日：2016-06-27

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hyun Cheol KOO ,  Hyung-jun KIM ,  Jun Woo CHOI ,  Joonyeon CHANG ,  Suk Hee HAN ,  Chaun JANG ,  Youn Ho PARK

IPC: H01L29/51 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/516 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66984 ,  H01L43/00

Abstract: Disclosed is a transistor including a topological insulator. The transistor includes: a substrate; a topological insulator provided on the substrate; a drain electrode provided on the topological insulator; a source electrode separated from the drain electrode, provided on the topological insulator, and including a ferromagnetic substance; a tunnel junction layer provided on the source electrode; and a gate electrode provided on the tunnel junction layer. A spin direction of the topological insulator is fixed by a current flowing to a surface thereof, and a spin direction of the source electrode is changed to a predetermined direction by a voltage applied to the gate electrode.

Abstract translation: 公开了包括拓扑绝缘体的晶体管。 晶体管包括：衬底; 设置在基板上的拓扑绝缘体; 设置在拓扑绝缘体上的漏电极; 与所述漏电极分离的源电极，设置在所述拓扑绝缘体上，并且包含铁磁性物质; 设置在源电极上的隧道结层; 以及设置在隧道结层上的栅电极。 拓扑绝缘体的自旋方向由流过其表面的电流固定，并且通过施加到栅电极的电压将源极的自旋方向改变到预定方向。

公开(公告)号：US20190287846A1

公开(公告)日：2019-09-19

申请号：US16282299

申请日：2019-02-22

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hyung-jun KIM ,  Sanghyeon KIM ,  Hansung KIM ,  Seong Kwang KIM ,  Hyeong Rak LIM

IPC: H01L21/762 ,  H01L21/683 ,  H01L21/02 ,  H01L21/78 ,  H01L29/06

Abstract: A method for manufacturing a semiconductor device according to embodiments may include forming a sacrificial layer on a first substrate including first dopant atoms and second dopant atoms, and forming a germanium (Ge) layer on the sacrificial layer. Here, the germanium (Ge) layer may include the first dopant atoms diffused from the first substrate by growth temperature in the forming step. Additionally, the method for manufacturing a semiconductor device may further include annealing after growth of the germanium (Ge) layer so that the germanium (Ge) layer may include second dopant atoms.

公开(公告)号：US20240200185A1

公开(公告)日：2024-06-20

申请号：US18501259

申请日：2023-11-03

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY ,  Inha University Research and Business Foundation

Inventor： Hyung-jun KIM ,  Rino CHOI ,  Seung-Hwan KIM ,  Daeyoon BAEK

IPC: C23C14/34

CPC classification number: C23C14/3414

Abstract: Provided is a method for manufacturing a multilayer structure. The method for manufacturing the multilayer structure includes providing a substrate in a chamber, providing a target in the chamber, and allowing a target material to be incident into the substrate so as to form a material layer. The target includes magnesium oxide or beryllium oxide. An incident angle of the target material to the substrate is about 9.14° or less.

公开(公告)号：US20230142462A1

公开(公告)日：2023-05-11

申请号：US17972912

申请日：2022-10-25

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hyung-jun KIM ,  Seunghwan KIM ,  Daeyoon BAEK

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/1033 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/045

Abstract: Embodiments relate to a semiconductor device including a trench with undercut structure including a substrate made of a first material; an insulation layer formed on an upper surface of the substrate; at least one trench penetrating the insulation layer toward the substrate; and at least one seed layer formed in the trench, the seed layer made of a second material which is different from the first material, and a method for manufacturing the same.

公开(公告)号：US20150333123A1

公开(公告)日：2015-11-19

申请号：US14508404

申请日：2014-10-07

Applicant: Korea Institute of Science and Technology

Inventor： Hyun Cheol KOO ,  Hyung-jun KIM ,  Joonyeon CHANG ,  Won Young CHOI ,  Suk Hee HAN

IPC: H01L29/12 ,  H01L29/06 ,  H01L29/16 ,  H01L29/82 ,  H01L29/205

CPC classification number: H01L29/122 ,  B82Y10/00 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1025 ,  H01L29/1606 ,  H01L29/205 ,  H01L29/66984 ,  H01L29/82 ,  H01L43/08

Abstract: A spin transistor includes: an input part that is made of a material exhibiting a spin Hall effect and configured to transfer electrons with a predetermined direction of spin to a connecting part; and the connecting part that receives the electrons with the predetermined direction of spin from the input part, rotates the spin of the electrons in accordance with a gate voltage applied to the gate electrode, and transfers the electrons to the output part.

Abstract translation: 自旋晶体管包括：输入部分，其由表现出自旋霍尔效应并被配置为将电子以预定旋转方向转移到连接部分的材料制成; 并且从输入部分接收具有预定旋转方向的电子的连接部分，根据施加到栅电极的栅极电压来旋转电子的自旋，并将电子传送到输出部分。

公开(公告)号：US20220238654A1

公开(公告)日：2022-07-28

申请号：US17583206

申请日：2022-01-25

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hyung-jun KIM ,  Seung Hwan KIM

IPC: H01L29/10 ,  H01L21/02

Abstract: Embodiments relate to a semiconductor device, which includes: a substrate made of a first material; an insulating layer formed on an upper surface of the substrate; a trench formed at the insulating layer to penetrate the insulating layer toward the substrate; and a seed layer disposed in the trench. The seed layer is made of a second material, the second material lattice-mismatches with respect to the first material, the seed layer includes a threading dislocation extending at least partially in a first direction non-parallel to the upper surface of the substrate and parallel to a direction of a (111) plane and a threading dislocation extending at least partially in a second direction, and the extension of the threading dislocation is terminated at a sidewall of the trench.

公开(公告)号：US20180350988A1

公开(公告)日：2018-12-06

申请号：US15955690

申请日：2018-04-18

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hyung-jun KIM ,  Sanghyeon KIM ,  Jae-Phil SHIM

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/16 ,  H01L29/66

Abstract: Disclosed is a semiconductor device, which includes: forming a first channel layer including a Group III-V compound or germanium (Ge) and having a first semiconductor characteristics on a first substrate; forming a second channel layer including a Group III-V compound or germanium (Ge) and having a second semiconductor characteristics different from the first semiconductor characteristics on the first channel layer; forming a bonding layer containing an oxide on a second channel layer; allowing the bonding layer to be bound to the second substrate so that a structure including the bonding layer, the second channel layer, the first channel layer and the first substrate may be stacked on the second substrate; removing the first substrate stacked on the second substrate; and removing the first channel layer from a partial region of the structure stacked on the second substrate.

公开(公告)号：US20180082900A1

公开(公告)日：2018-03-22

申请号：US15631309

申请日：2017-06-23

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Sanghyeon KIM ,  Hyung-jun KIM ,  Jae-Phil SHIM ,  Seong Kwang KIM ,  Won Jun CHOI

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/7813 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/30617

Abstract: A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.