公开(公告)号：US20110124164A1

公开(公告)日：2011-05-26

申请号：US12949283

申请日：2010-11-18

申请人： Kosei NODA ,  Toshihiko TAKEUCHI ,  Makoto ISHIKAWA

发明人： Kosei NODA ,  Toshihiko TAKEUCHI ,  Makoto ISHIKAWA

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/268 ,  H01L21/84 ,  H01L29/0696 ,  H01L29/456 ,  H01L29/66681 ,  H01L29/7824 ,  H01L31/022425 ,  H01L31/02245 ,  H01L31/0747 ,  H01L31/075 ,  H01L31/1804 ,  H01L31/1892 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： An amorphous semiconductor layer is formed over a first single crystal semiconductor layer provided over a glass substrate or a plastic substrate with an insulating layer therebetween. The amorphous semiconductor layer is formed by a CVD method at a deposition temperature of higher than or equal to 100° C. and lower than or equal to 275° C. with use of a silane-based gas not diluted. Heat treatment is performed so that the amorphous semiconductor layer solid-phase epitaxially grows. In such a manner, an SOI substrate including a thick single crystal semiconductor layer is manufactured.

摘要翻译： 在设置在玻璃基板上的第一单晶半导体层或其间具有绝缘层的塑料基板上形成非晶半导体层。 使用未稀释的硅烷类气体，通过CVD法在高于或等于100℃且低于或等于275℃的沉积温度下形成非晶半导体层。 进行热处理，使得非晶半导体层固相外延生长。 以这种方式制造包括厚单晶半导体层的SOI衬底。

公开(公告)号：US20120248432A1

公开(公告)日：2012-10-04

申请号：US13423468

申请日：2012-03-19

申请人： Kosei NODA ,  Noriyoshi SUZUKI

发明人： Kosei NODA ,  Noriyoshi SUZUKI

IPC分类号： H01L29/786 ,  H01L21/36

CPC分类号： H01L29/7869 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02664 ,  H01L29/42384 ,  H01L29/66969

摘要： A highly reliable semiconductor device having stable electric characteristics is provided by suppressing, in a transistor including an oxide semiconductor film, diffusion of indium into an insulating film in contact with the oxide semiconductor film and improving the characteristics of the interface between the oxide semiconductor film and the insulating film. In an oxide semiconductor film containing indium, the indium concentration at a surface is decreased, thereby preventing diffusion of indium into an insulating film on and in contact with the oxide semiconductor film. By decreasing the indium concentration at the surface of the oxide semiconductor film, a layer which does not substantially contain indium can be formed at the surface. By using this layer as part of the insulating film, the characteristics of the interface between the oxide semiconductor film and the insulating film in contact with the oxide semiconductor film are improved.

摘要翻译： 通过在包括氧化物半导体膜的晶体管中抑制铟扩散到与氧化物半导体膜接触的绝缘膜中，提高了具有稳定电特性的高度可靠的半导体器件，并且改善了氧化物半导体膜与氧化物半导体膜之间的界面的特性 绝缘膜。 在含有铟的氧化物半导体膜中，表面的铟浓度降低，从而防止铟在氧化物半导体膜上与绝缘膜的扩散接触。 通过降低氧化物半导体膜表面的铟浓度，可以在表面形成实质上不含有铟的层。 通过使用该层作为绝缘膜的一部分，改善了与氧化物半导体膜接触的氧化物半导体膜与绝缘膜之间的界面的特性。

公开(公告)号：US20120228605A1

公开(公告)日：2012-09-13

申请号：US13410604

申请日：2012-03-02

申请人： Kosei NODA

发明人： Kosei NODA

IPC分类号： H01L29/786 ,  H01L29/22 ,  H01L21/44

CPC分类号： H01L29/66742 ,  H01L27/1156 ,  H01L27/1207 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

摘要： A semiconductor device includes an oxide semiconductor film including a pair of first regions, a pair of second regions, and a third region; a pair of electrodes in contact with the oxide semiconductor film; a gate insulating film over the oxide semiconductor film; and a gate electrode provided between the pair of electrodes with the gate insulating film interposed therebetween. The pair of first regions overlap with the pair of electrodes, the third region overlaps with the gate electrode, and the pair of second regions are formed between the pair of first regions and the third region. The pair of second regions and the third region each contain nitrogen, phosphorus, or arsenic. The pair of second regions have a higher element concentration than the third region.

摘要翻译： 半导体器件包括包括一对第一区域，一对第二区域和第三区域的氧化物半导体膜; 与氧化物半导体膜接触的一对电极; 氧化物半导体膜上的栅极绝缘膜; 以及设置在所述一对电极之间的栅电极，其间插入有所述栅极绝缘膜。 所述一对第一区域与所述一对电极重叠，所述第三区域与所述栅电极重叠，并且所述一对第二区域形成在所述一对第一区域与所述第三区域之间。 一对第二区域和第三区域各自含有氮，磷或砷。 一对第二区域具有比第三区域更高的元件浓度。

公开(公告)号：US20120119212A1

公开(公告)日：2012-05-17

申请号：US13289436

申请日：2011-11-04

申请人： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA

发明人： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66969 ,  H01L21/02 ,  H01L21/02112 ,  H01L21/02403 ,  H01L21/28 ,  H01L21/425 ,  H01L21/477 ,  H01L29/42384 ,  H01L29/518 ,  H01L29/78618 ,  H01L29/7869

摘要： A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

摘要翻译： 使用其中氧化物半导体包括在沟道区域中的晶体管制造半导体器件，并且不太可能引起由于短沟道效应引起的电特性的变化。 半导体器件包括具有一对氧氮化物半导体区域的氧化物半导体膜，该氧氮化物半导体区域包括氮和夹在一对氧氮化物半导体区域之间的氧化物半导体区域，栅极绝缘膜和设置在氧化物半导体区域上的栅电极，栅极绝缘 胶片位于其间。 这里，一对氧氮化物半导体区域用作晶体管的源极区域和漏极区域，氧化物半导体区域用作晶体管的沟道区域。

公开(公告)号：US20110204368A1

公开(公告)日：2011-08-25

申请号：US13026511

申请日：2011-02-14

申请人： Masashi TSUBUKU ,  Kosei NODA

发明人： Masashi TSUBUKU ,  Kosei NODA

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L27/156

摘要： The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap or less than or equal to the band gap is reduced. In that case, not by merely optimizing conditions of manufacturing an oxide semiconductor film, but by making an oxide semiconductor to be a substantially intrinsic semiconductor or extremely close to an intrinsic semiconductor, defects on which irradiation light acts are reduced and the effect of light irradiation is reduced essentially. That is, even in the case where light with a wavelength of 350 nm is delivered at 1×1013 photons/cm2·sec, a channel region of a transistor is formed using an oxide semiconductor, in which the absolute value of the amount of the variation in the threshold voltage is less than or equal to 0.65 V.

摘要翻译： 频带尾部状态和带隙中的缺陷尽可能地减小，由此减小了在带隙附近或小于或等于带隙的能量的光吸收。 在这种情况下，不是仅通过优化氧化物半导体膜的制造条件，而是通过使氧化物半导体成为本质上的本征半导体，或者非常接近本征半导体，减少照射光的作用的缺陷和光照射 基本上减少了。 也就是说，即使在以1×1013个光子/ cm 2·sec传递波长为350nm的光的情况下，也可以使用氧化物半导体形成晶体管的沟道区域，其中， 阈值电压的变化小于或等于0.65 V.

公开(公告)号：US20100184269A1

公开(公告)日：2010-07-22

申请号：US12684269

申请日：2010-01-08

申请人： Kosei NODA

发明人： Kosei NODA

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： To provide a method for manufacturing a semiconductor substrate provided with a single crystal semiconductor layer which can be used practically even when a substrate with a low upper temperature limit, such as a glass substrate, is used. An oxide film is formed on a single crystal semiconductor substrate; accelerated ions are introduced into the single crystal semiconductor substrate through the oxide film to form an embrittled region in the single crystal semiconductor substrate; a supporting substrate is bonded such that the supporting substrate and the single crystal semiconductor substrate face each other with the oxide film interposed therebetween; separation is performed at the embrittled region into the supporting substrate to which a single crystal semiconductor layer is bonded and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; first etching is performed on a surface of the single crystal semiconductor layer bonded to the supporting substrate with a substrate bias applied; the single crystal semiconductor layer is irradiated with a laser beam and at least part of the surface of the single crystal semiconductor layer is melted and solidified; and second etching is performed on the surface of the single crystal semiconductor layer with no substrate bias applied.

摘要翻译： 为了提供一种制造具有单晶半导体层的半导体衬底的方法，即使使用诸如玻璃衬底的上限温度低的衬底也可以实际使用。 在单晶半导体基板上形成氧化膜; 加速离子通过氧化膜被引入到单晶半导体衬底中，以在单晶半导体衬底中形成脆化区; 支撑基板被接合，使得支撑基板和单晶半导体基板彼此面对，氧化膜插入其间; 通过单晶半导体衬底的加热，在脆化区域进行与单晶半导体层接合的支撑衬底和部分单晶半导体衬底的分离; 在施加了衬底偏压的情况下，在结合到支撑衬底的单晶半导体层的表面上进行第一蚀刻; 用激光束照射单晶半导体层，并且使单晶半导体层的表面的至少一部分熔融固化; 并且在不施加衬底偏压的情况下对单晶半导体层的表面进行第二蚀刻。

公开(公告)号：US20130230772A1

公开(公告)日：2013-09-05

申请号：US13596189

申请日：2012-08-28

申请人： Kosei NODA ,  Kazutaka KURIKI ,  Nobuhiro INOUE

发明人： Kosei NODA ,  Kazutaka KURIKI ,  Nobuhiro INOUE

IPC分类号： H01G11/68 ,  H01M4/38 ,  H01G11/06 ,  H01M4/48

CPC分类号： H01G11/68 ,  H01G11/06 ,  H01G11/28 ,  H01G11/30 ,  H01G11/46 ,  H01G11/86 ,  H01M4/131 ,  H01M4/134 ,  H01M4/1391 ,  H01M4/1395 ,  H01M4/366 ,  H01M4/386 ,  H01M4/387 ,  H01M4/48 ,  H01M4/483 ,  H01M10/052 ,  Y02E60/13 ,  Y02T10/7011 ,  Y02T10/7022

摘要： As an electrode for a power storage device, an electrode including a current collector, a first active material layer over the current collector, and a second active material layer that is over the first active material layer and includes a particle containing niobium oxide and a granular active material is used, whereby the charge-discharge cycle characteristics and rate characteristics of the power storage device can be improved. Moreover, contact between the granular active material and the particle containing niobium oxide makes the granular active material physically fixed; accordingly, deterioration due to expansion and contraction of the active material which occur along with charge and discharge of the power storage device, such as powdering of the active material or its separation from the current collector, can be suppressed.

摘要翻译： 作为蓄电装置的电极，包括集电体，集电体上方的第一活性物质层和超过第一活性物质层的第二活性物质层的电极，包括含有氧化铌的颗粒和粒状的 使用活性物质，能够提高蓄电装置的充放电循环特性和速率特性。 此外，颗粒状活性物质与含有氧化铌的粒子的接触使粒状活性物质物理固定; 因此，可以抑制由于蓄电装置的充放电而发生的活性物质的膨胀和收缩的劣化，例如活性物质的粉化或其与集电器的分离。

公开(公告)号：US20120299003A1

公开(公告)日：2012-11-29

申请号：US13568186

申请日：2012-08-07

申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

IPC分类号： H01L29/22 ,  H01L27/15 ,  H01L29/786

CPC分类号： H01L27/1225 ,  H01L21/823412 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/156 ,  H01L27/3213 ,  H01L29/24 ,  H01L29/36 ,  H01L29/7869 ,  H01L29/78693 ,  H01L33/025 ,  H01L2924/0002 ,  H04M1/0266 ,  H04R1/02 ,  H01L2924/00

摘要： An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

摘要翻译： 目的是获得使用其中使用氧化物半导体层的薄膜晶体管，在检测信号和宽动态范围中具有高灵敏度的半导体器件。 使用具有作为沟道形成层的功能的氧化物半导体的薄膜晶体管形成模拟电路，其氢浓度为5×1019个原子/ cm3以下，并且在该状态下基本上起绝缘体的作用 其中不产生电场。 因此，可以获得在检测信号中具有高灵敏度和宽动态范围的半导体器件。

公开(公告)号：US20120273774A1

公开(公告)日：2012-11-01

申请号：US13448609

申请日：2012-04-17

申请人： Kosei NODA

发明人： Kosei NODA

IPC分类号： H01L29/12

CPC分类号： H01L27/0688 ,  H01L21/823807 ,  H01L21/8258 ,  H01L29/4236 ,  H01L29/42384 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7869 ,  H01L29/78696

摘要： The semiconductor device includes transistors which are stacked. The transistors include a semiconductor substrate having a groove portion and a pair of low-resistance regions between which the groove portion is provided, a first gate insulating film over the semiconductor substrate, a gate electrode overlapping with the groove portion with the first gate insulating film interposed therebetween, a second gate insulating film covering the gate electrode, a pair of electrodes provided over the second gate insulating film so that the groove portion is sandwiched between the pair of electrodes, and a semiconductor film in contact with the pair of electrodes. One of the pair of low-resistance region is electrically connected to one of the pair of electrodes. One of the transistors includes an n-type semiconductor and the other includes a p-type semiconductor, so that a complementary MOS circuit is formed.

摘要翻译： 半导体器件包括堆叠的晶体管。 晶体管包括具有沟槽部分和一对低电阻区域的半导体衬底，在该半导体衬底之间设置有沟槽部分，半导体衬底上的第一栅极绝缘膜，与沟槽部分重叠的栅电极与第一栅极绝缘膜 介于其间的第二栅极绝缘膜，覆盖所述栅电极的第二栅极绝缘膜，设置在所述第二栅极绝缘膜上的一对电极，使得所述沟槽部分夹在所述一对电极之间，以及与所述一对电极接触的半导体膜。 一对低电阻区域中的一个电连接到该对电极中的一个。 晶体管中的一个包括n型半导体，另一个包括p型半导体，从而形成互补MOS电路。

公开(公告)号：US20120223310A1

公开(公告)日：2012-09-06

申请号：US13402194

申请日：2012-02-22

申请人： Kosei NODA ,  Yuta ENDO

发明人： Kosei NODA ,  Yuta ENDO

IPC分类号： H01L29/786 ,  H01L21/20

CPC分类号： H01L27/10873 ,  H01L21/02554 ,  H01L21/02565 ,  H01L27/10805 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

摘要： A semiconductor memory device includes a transistor and a capacitor. The transistor includes: an insulating film in which a groove portion is provided; a pair of electrodes separated so that the groove portion is sandwiched therebetween; an oxide semiconductor film which is in contact with the pair of electrodes and side surfaces and a bottom surface of the groove portion and has a thickness value smaller than a depth value of the groove portion; a gate insulating film covering the oxide semiconductor film; and a gate electrode provided to overlap with the oxide semiconductor film with the gate insulating film positioned therebetween.

摘要翻译： 半导体存储器件包括晶体管和电容器。 晶体管包括：设置有沟槽部分的绝缘膜; 一对电极被分离，使得沟槽部分夹在其间; 与所述一对电极和侧面接触的氧化物半导体膜和所述槽部的底面，并且具有比所述槽部的深度值小的厚度值。 覆盖氧化物半导体膜的栅极绝缘膜; 以及设置成与氧化物半导体膜重叠的栅电极，栅极绝缘膜位于它们之间。