公开(公告)号：US20050110127A1

公开(公告)日：2005-05-26

申请号：US10981489

申请日：2004-11-05

申请人： Kouichi Kanemoto ,  Kazunari Suzuki ,  Toshihiro Shiotsuki ,  Hideyuki Suga

发明人： Kouichi Kanemoto ,  Kazunari Suzuki ,  Toshihiro Shiotsuki ,  Hideyuki Suga

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/12 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L29/423

CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A thin semiconductor device which assures a high production yield. The semiconductor device includes: first and second semiconductor chips each of which has electrodes over its first surface; first leads electrically connected with the electrodes of the first semiconductor chip through first bonding wires; second leads electrically connected with the electrodes of the second semiconductor chip through second bonding wires; a die pad with first and second surfaces opposite each other where the first semiconductor chip's first surface is bonded to the first surface and the second semiconductor chip's first surface is bonded to the second surface; and a resin sealer which seals the first and second semiconductor chips, inner portions of the first and second leads, the first and second bonding wires, and the die pad. The inner portions of the first and second leads and the die pad lie at the same height level in a thickness direction of the resin sealer.

摘要翻译： 确保高产量的薄半导体器件。 半导体器件包括：第一和第二半导体芯片，每个半导体芯片在其第一表面上具有电极; 第一引线通过第一接合线与第一半导体芯片的电极电连接; 第二引线通过第二接合线与第二半导体芯片的电极电连接; 具有第一和第二表面相对的第一和第二表面的第一和第二表面，其中第一半导体芯片的第一表面接合到第一表面，并且第二半导体芯片的第一表面接合到第二表面; 以及密封第一和第二半导体芯片，第一和第二引线的内部部分，第一和第二接合线以及管芯焊盘的树脂密封件。 第一和第二引线和芯片焊盘的内部在树脂密封件的厚度方向处于相同的高度水平。

公开(公告)号：US06531773B2

公开(公告)日：2003-03-11

申请号：US09930942

申请日：2001-08-17

申请人： Hirotaka Nishizawa ,  Masachika Masuda ,  Kouichi Kanemoto ,  Tamaki Wada

发明人： Hirotaka Nishizawa ,  Masachika Masuda ,  Kouichi Kanemoto ,  Tamaki Wada

IPC分类号： H01L2334

CPC分类号： H01L24/49 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01039 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside of the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.

公开(公告)号：US06492727B2

公开(公告)日：2002-12-10

申请号：US09930943

申请日：2001-08-17

申请人： Hirotaka Nishizawa ,  Masachika Masuda ,  Kouichi Kanemoto ,  Tamaki Wada

发明人： Hirotaka Nishizawa ,  Masachika Masuda ,  Kouichi Kanemoto ,  Tamaki Wada

IPC分类号： H01L2334

CPC分类号： H01L24/49 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01039 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside of the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.

公开(公告)号：US06924547B2

公开(公告)日：2005-08-02

申请号：US10443956

申请日：2003-05-23

申请人： Kouichi Kanemoto ,  Masachika Masuda

发明人： Kouichi Kanemoto ,  Masachika Masuda

IPC分类号： B42D15/10 ,  G06K19/077 ,  H01L21/56 ,  H01L23/28 ,  H01L23/498 ,  H01L25/065 ,  H01L23/495

CPC分类号： G06K19/07732 ,  G06K19/077 ,  H01L23/49855 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory card is disclosed which not only suppresses a lowering of the manufacturing yield caused by warping of a semiconductor chip sealing member, but also reduces the manufacturing cost by using a less expensive material. The memory card comprises a thin plate-like cap formed of a synthetic resin and a sealing member mounted inside the cap. Inside the sealing member are sealed a metallic lead frame and three semiconductor chips (two memory chips and one control chip) mounted on part (leads) of the lead frame. The semiconductor chips are electrically connected to leads through Au wires. Connecting terminals integral with the lead frame are exposed to the back side of the sealing member.

摘要翻译： 公开了一种存储卡，其不仅抑制了由半导体芯片密封构件的翘曲引起的制造成品率的降低，而且还通过使用较便宜的材料来降低制造成本。 存储卡包括由合成树脂形成的薄板状盖和安装在盖内的密封构件。 在密封构件内密封金属引线框架和安装在引线框架的一部分（引线）上的三个半导体芯片（两个存储器芯片和一个控制芯片）。 半导体芯片通过Au线电连接到引线。 与引线框一体的连接端子暴露于密封构件的背面。

公开(公告)号：US06501183B2

公开(公告)日：2002-12-31

申请号：US09915375

申请日：2001-07-27

申请人： Kouichi Kanemoto ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Mikako Kimura

发明人： Kouichi Kanemoto ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Mikako Kimura

IPC分类号： H01L2348

CPC分类号： H01L21/6836 ,  H01L21/565 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68327 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01028 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A first semiconductor chip (2) is bonded and secured to a second semiconductor chip (3) with a back surface of the first semiconductor chip (2) and a circuit forming surface (3X) of the second semiconductor chip (3) facing each other, and an inner portion of a support lead (6) is bonded and secured to the circuit forming surface (3X) of the second semiconductor chip (3). Such a configuration makes it possible to provide a semiconductor with a reduced thickness.

摘要翻译： 第一半导体芯片（2）被接合并固定到具有第一半导体芯片（2）的背面的第二半导体芯片（3）和第二半导体芯片（3）的彼此面对的电路形成表面（3X） ，并且支撑引线（6）的内部部分被接合并固定到第二半导体芯片（3）的电路形成表面（3X）。 这种构造使得可以提供具有减小的厚度的半导体。

公开(公告)号：US06501173B2

公开(公告)日：2002-12-31

申请号：US09797719

申请日：2001-03-05

申请人： Hirotaka Nishizawa ,  Masachika Masuda ,  Kouichi Kanemoto ,  Tamaki Wada

发明人： Hirotaka Nishizawa ,  Masachika Masuda ,  Kouichi Kanemoto ,  Tamaki Wada

IPC分类号： H01L2334

CPC分类号： H01L24/49 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01039 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.

摘要翻译： 提出了当多个半导体芯片被密封在单个树脂密封体中时考虑促进半导体芯片的测试的芯片安装方法。 该方法还考虑其应用于各种MCP和系统LSI。 在单个封装中，第一半导体芯片的一个信号输出端子和半导体器件的第一外部端子独立地内部连接。 第二半导体芯片的一个信号输入端子和半导体器件的第二外部端子独立地内部连接。 半导体器件的第一和第二外部端子连接在半导体器件外部，以完成信号输出端子与信号输入端子之间的连接。

公开(公告)号：US07552876B2

公开(公告)日：2009-06-30

申请号：US11924044

申请日：2007-10-25

申请人： Hirotaka Nishizawa ,  Haruji Ishihara ,  Atsushi Shiraishi ,  Kouichi Kanemoto ,  Yousuke Yukawa

发明人： Hirotaka Nishizawa ,  Haruji Ishihara ,  Atsushi Shiraishi ,  Kouichi Kanemoto ,  Yousuke Yukawa

IPC分类号： G06K19/06

CPC分类号： G06K19/07732 ,  G06K19/07743 ,  G11C5/066 ,  H01L25/18 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2225/06562 ,  H01L2924/01021 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/117 ,  H01L2924/00 ,  H01L2924/00012

摘要： An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.

摘要翻译： IC卡具有安装在其上的半导体集成电路芯片的卡片基板和形成在其上的多个连接器端子。 连接器端子从壳体露出。 连接器端子以IC卡插入方向观察时以相互相邻的序列之间的交错形式以多个顺序布置。 由于采用交错布局，所以可以相对容易地采用其中插座插座的插座端子的突出量改变并且插座端子串联布置的结构或配置。 如果采用向下或低阶IC卡的连接器端子排列作为特定的连接器端子序列，而专门用于向上或高位IC卡的功能被分配给另一个交错的连接器端子装置，则向后 兼容性也可以轻松实现。

公开(公告)号：US20080257968A1

公开(公告)日：2008-10-23

申请号：US11924044

申请日：2007-10-25

申请人： Hirotaka Nishizawa ,  Haruji Ishihara ,  Atsushi Shiraishi ,  Kouichi Kanemoto ,  Yousuke Yukawa

发明人： Hirotaka Nishizawa ,  Haruji Ishihara ,  Atsushi Shiraishi ,  Kouichi Kanemoto ,  Yousuke Yukawa

IPC分类号： G06K19/06

CPC分类号： G06K19/07732 ,  G06K19/07743 ,  G11C5/066 ,  H01L25/18 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2225/06562 ,  H01L2924/01021 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/117 ,  H01L2924/00 ,  H01L2924/00012

摘要： An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.

摘要翻译： IC卡具有安装在其上的半导体集成电路芯片的卡片基板和形成在其上的多个连接器端子。 连接器端子从壳体露出。 连接器端子以IC卡插入方向观察时以相互相邻的序列之间的交错形式以多个顺序布置。 由于采用交错布局，所以可以相对容易地采用其中插座插座的插座端子的突出量改变并且插座端子串联布置的结构或配置。 如果采用向下或低阶IC卡的连接器端子排列作为特定的连接器端子序列，而专门用于向上或高位IC卡的功能被分配给另一个交错的连接器端子装置，则向后 兼容性也可以轻松实现。

公开(公告)号：US07234644B2

公开(公告)日：2007-06-26

申请号：US11378277

申请日：2006-03-20

申请人： Hirotaka Nishizawa ,  Haruji Ishihara ,  Atsushi Shiraishi ,  Kouichi Kanemoto ,  Yousuke Yukawa

发明人： Hirotaka Nishizawa ,  Haruji Ishihara ,  Atsushi Shiraishi ,  Kouichi Kanemoto ,  Yousuke Yukawa

IPC分类号： G06K19/06 ,  G06K7/06

CPC分类号： G06K19/07732 ,  G06K19/07743 ,  G11C5/066 ,  H01L25/18 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2225/06562 ,  H01L2924/01021 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/117 ,  H01L2924/00 ,  H01L2924/00012

摘要： An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.

摘要翻译： IC卡具有安装在其上的半导体集成电路芯片的卡片基板和形成在其上的多个连接器端子。 连接器端子从壳体露出。 连接器端子以IC卡插入方向观察时以相互相邻的序列之间的交错形式以多个顺序布置。 由于采用交错布局，所以可以相对容易地采用其中插座插座的插座端子的突出量改变并且插座端子串联布置的结构或配置。 如果采用向下或低阶IC卡的连接器端子排列作为特定的连接器端子序列，而专门用于向上或高位IC卡的功能被分配给另一个交错的连接器端子装置，则向后 兼容性也可以轻松实现。

公开(公告)号：US06945465B2

公开(公告)日：2005-09-20

申请号：US09756867

申请日：2001-01-10

申请人： Hirotaka Nishizawa ,  Haruji Ishihara ,  Atsushi Shiraishi ,  Kouichi Kanemoto ,  Yousuke Yukawa

发明人： Hirotaka Nishizawa ,  Haruji Ishihara ,  Atsushi Shiraishi ,  Kouichi Kanemoto ,  Yousuke Yukawa

IPC分类号： G06K19/07 ,  B42D15/10 ,  G06K19/073 ,  G06K19/077 ,  H05K1/11 ,  G06K19/06

CPC分类号： G06K19/07732 ,  G06K19/07743 ,  G11C5/066 ,  H01L25/18 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2225/06562 ,  H01L2924/01021 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/117 ,  H01L2924/00 ,  H01L2924/00012

摘要： An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.

摘要翻译： IC卡具有安装在其上的半导体集成电路芯片的卡片基板和形成在其上的多个连接器端子。 连接器端子从壳体露出。 连接器端子以IC卡插入方向观察时以相互相邻的序列之间的交错形式以多个顺序布置。 由于采用交错布局，所以可以相对容易地采用其中插座插座的插座端子的突出量改变并且插座端子串联布置的结构或配置。 如果采用向下或低阶IC卡的连接器端子排列作为特定的连接器端子序列，而专门用于向上或高位IC卡的功能被分配给另一个交错的连接器端子装置，则向后 兼容性也可以轻松实现。