公开(公告)号：US5642252A

公开(公告)日：1997-06-24

申请号：US288729

申请日：1994-08-15

申请人： Kozo Sakamoto ,  Isao Yoshida ,  Shigeo Otaka ,  Tetsuo Iijima ,  Harutora Shono ,  Ken Uchid ,  Masayoshi Kobayashi ,  Hideki Tsunoda

发明人： Kozo Sakamoto ,  Isao Yoshida ,  Shigeo Otaka ,  Tetsuo Iijima ,  Harutora Shono ,  Ken Uchid ,  Masayoshi Kobayashi ,  Hideki Tsunoda

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/78 ,  H02H5/04 ,  H03K17/08 ,  H03K17/082 ,  H02H3/00

CPC分类号： H03K17/0822 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/7803 ,  H01L29/7804 ,  H02H5/044 ,  H01L29/0696 ,  H03K2017/0806

摘要： An improvement in conditions that protective functions of an insulated gate semiconductor device with a protection circuit incorporated therein are performed, an improvement in the cutoff of heating, the prevention of malfunctions and an improvement in ease of usage can be achieved.The insulated gate semiconductor device of the present invention comprises a power insulated gate semiconductor element (M9), at least one MOSFET (M1 through M7) for a protection circuit, for controlling the power insulated gate semiconductor element, a constant-voltage circuit using forward voltages developed across diodes (D2a through D2f) for the constant-voltage circuit, and voltage restricting diodes (D1 and D0a through D0d) for controlling the upper limit of a power supply voltage of the constant-voltage circuit. Power to be supplied to the voltage restricting diodes is supplied from an external gate terminal of the power insulated gate semiconductor element.The present invention can bring about an advantageous effect that an improvement in reliability of the insulated gate semiconductor device and an improvement in the ease of use can be achieved.

摘要翻译： 可以实现具有并入其中的保护电路的绝缘栅半导体器件的保护功能的条件的改善，可以提高加热截止，防止故障和提高易用性。 本发明的绝缘栅半导体器件包括功率绝缘栅极半导体元件（M9），用于保护电路的至少一个MOSFET（M1至M7），用于控制功率绝缘栅极半导体元件，使用正向的恒压电路 用于恒压电路的二极管（D2a至D2f）上产生的电压以及用于控制恒压电路的电源电压的上限的电压限制二极管（D1和D0a至D0d）。 供电到限压二极管的功率从功率绝缘栅极半导体元件的外部栅极端子提供。 本发明可以实现提高绝缘栅极半导体器件的可靠性和提高易用性的有利效果。

公开(公告)号：US5638246A

公开(公告)日：1997-06-10

申请号：US10572

申请日：1993-01-28

申请人： Kozo Sakamoto ,  Isao Yoshida ,  Masatoshi Morikawa ,  Shigeo Ohtaka ,  Hideki Tsunoda

发明人： Kozo Sakamoto ,  Isao Yoshida ,  Masatoshi Morikawa ,  Shigeo Ohtaka ,  Hideki Tsunoda

IPC分类号： H02H5/04 ,  H03K17/08 ,  H03K17/082

CPC分类号： H02H5/044 ,  H03K17/0822 ,  H03K2017/0806

摘要： In a semiconductor device including a power MOSFET (M.sub.0) for the output stage, a temperature detection circuit produces an output signal upon detecting an abnormal rise in the chip temperature, the signal turns on a set input element (M.sub.1) in a latch circuit so that the latch circuit becomes a set state, the set output of the latch circuit turns on a control element (M.sub.5), causing the power MOSFET to become non-conductive so that it is protected from destruction. The latch circuit is not brought to a reset state even if the external gate terminal of the device is brought to zero volt. With a voltage outside the range of the normal input signal, e.g., a large negative voltage, being applied to the external gate terminal, the gate capacitance of the control element (M.sub.5) discharges, and consequently the latch circuit is brought to the reset state and the protective operation is cancelled. The semiconductor device is further provided with an external reset terminal, and the protective operation can also be cancelled through the application of a reset signal to the external reset terminal. The semiconductor device is protected from destruction and also from deterioration of characteristics of the power MOSFET (M.sub.0), and yet the protective operation is not cancelled erroneously by the normal input signal.

摘要翻译： 在包括用于输出级的功率MOSFET（M0）的半导体器件中，温度检测电路在检测到芯片温度的异常升高时产生输出信号，该信号使锁存电路中的设定输入元件（M1）接通，从而 锁存电路变为置位状态，锁存电路的设定输出导通控制元件（M5），使功率MOSFET变得不导通，从而防止其破坏。 即使器件的外部栅极端子达到零伏，锁存电路也不会进入复位状态。 在外部栅极端子施加正常输入信号（例如，大的负电压）的范围之外的电压时，控制元件（M5）的栅极电容放电，因此锁存电路进入复位状态 并且保护操作被取消。 半导体器件还具有外部复位端子，并且还可以通过向外部复位端子施加复位信号来取消保护操作。 保护半导体器件不受破坏，也可以防止功率MOSFET（M0）的特性恶化，而保护操作也不会被正常输入信号错误地消除。

公开(公告)号：US5629542A

公开(公告)日：1997-05-13

申请号：US571766

申请日：1995-12-13

申请人： Kozo Sakamoto ,  Shigeo Otaka ,  Kyouichi Takagawa

发明人： Kozo Sakamoto ,  Shigeo Otaka ,  Kyouichi Takagawa

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/06 ,  H03K17/082 ,  H03K19/003 ,  H03K19/0944 ,  H03K19/173 ,  H01L27/02

CPC分类号： H03K17/0822 ,  H01L27/0629 ,  H01L2924/0002

摘要： Provided is a compounded power MOSFET which has a high positive and negative withstand voltages for the drain terminal relative to the source terminal, and can be formed on a single chip based on the conventional fabrication process of power MOSFETs. Power MOSFETs 10 and 11 have their drains connected together, the MOSFET 10 has its source and gate used for the source terminal 0 and gate terminal 1, respectively, of the compounded power MOSFET 60, and the MOSFET 11 has its source used for the drain terminal 2. The compounded power MOSFET includes a voltage comparator 50 which drives the MOSFET 11 to turn off when the terminal 2 has a negative voltage, and a voltage transmitter 51 which is connected between the terminal 1 and the gate of the MOSFET 11 to block a current flowing from the terminal 2 to the terminal 1 by way of the circuit 50 and transfer the voltage of the terminal 1 to the gate of the MOSFET 11. The positive withstand voltage is provided by the MOSFET 10, and the negative withstand voltage is provided by the MOSFET 11.

摘要翻译： 提供了一种复合功率MOSFET，其具有用于漏极端子相对于源极端子的高的正和负的耐受电压，并且可以基于功率MOSFET的常规制造工艺在单个芯片上形成。 功率MOSFET 10和11的漏极连接在一起，MOSFET 10的源极和栅极分别用于复合功率MOSFET 60的源极端子0和栅极端子1，并且MOSFET 11的源极用于漏极 复合功率MOSFET包括电压比较器50，其在端子2具有负电压时驱动MOSFET 11截止;以及电压发射器51，其连接在端子1和MOSFET 11的栅极之间以阻塞 通过电路50从端子2流到端子1的电流，并将端子1的电压传递到MOSFET 11的栅极。正极耐受电压由MOSFET10提供，负的耐压是 由MOSFET 11提供。

公开(公告)号：US06385025B2

公开(公告)日：2002-05-07

申请号：US09797983

申请日：2001-03-05

申请人： Kozo Sakamoto ,  Isao Yoshida

发明人： Kozo Sakamoto ,  Isao Yoshida

IPC分类号： H02H300

CPC分类号： H03K17/0828 ,  H03K17/0822 ,  H03K2017/0806

摘要： A semiconductor apparatus such as a power MOSFET, an IGBT, or the like is provided having therein a control circuit such as an over-heating protection circuit and an over-current protection circuit, which realizes both of high-speed operation and prevention of erroneous operation caused by a parasitic device. To prevent erroneous operation, the control circuit controls so that when the voltage of a gate terminal is positive relative to that of a source terminal, a first switch circuit is turned on, when the voltage of the gate terminal is negative relative to that of the source terminal, a second switch circuit is turned on, and when the gate terminal and the source terminal have an almost same potential and a drain terminal has a high potential, the second switch circuit is turned on, thereby reducing leakage current from the drain terminal to the gate terminal.

摘要翻译： 提供诸如功率MOSFET，IGBT等的半导体装置，其中具有诸如过热保护电路和过电流保护电路的控制电路，其实现高速操作和防止错误 由寄生器件引起的操作。 为了防止错误操作，控制电路进行控制，使得当栅极端子的电压相对于源极端子的电压为正时，第一开关电路导通，当栅极端子的电压相对于栅极端子的电压为负时 源极端子，第二开关电路导通，并且当栅极端子和源极端子具有几乎相同的电位且漏极端子具有高电位时，第二开关电路导通，从而减少漏极端子的漏电流 到门终端。

公开(公告)号：US06201677B1

公开(公告)日：2001-03-13

申请号：US09489736

申请日：2000-01-21

申请人： Kozo Sakamoto ,  Isao Yoshida

发明人： Kozo Sakamoto ,  Isao Yoshida

IPC分类号： H02H308

CPC分类号： H03K17/0828 ,  H03K17/0822 ,  H03K2017/0806

摘要： There is disclosed a semiconductor apparatus such as a power MOSFET, an IGBT, or the like having therein a control circuit such as an over-heating protection circuit and an over-current protection circuit, which realizes both of high-speed operation and prevention of erroneous operation caused by a parasitic device. In order to prevent erroneous operation of a power MOSFET 30 and a protection circuit 21 caused by a parasitic npn transistor 29 of an MOSFET 32, a control circuit 20 controls so that when the voltage of a gate terminal 2 is positive relative to that of a source terminal 3, a switch circuit SW3 is turned on, when the voltage of the gate terminal 2 is negative relative to that of the source terminal 3, a switch circuit SW2 is turned on, and when the gate terminal 2 and the source terminal 3 have an almost same potential and a drain terminal 1 has a high potential, the switch circuit SW2 is turned on. By adding such a control circuit, an insulated gate semiconductor apparatus having therein the protection circuit according to the invention can reduce a leakage current flowing from the drain terminal to the gate terminal when a negative voltage is applied to the gate and can operate at high speed without causing drop of a drain breakdown voltage.

摘要翻译： 公开了具有诸如过热保护电路和过电流保护电路等控制电路的功率MOSFET，IGBT等半导体装置，实现了高速运行和防止 由寄生器件引起的错误操作。为了防止由MOSFET32的寄生npn晶体管29引起的功率MOSFET 30和保护电路21的错误操作，控制电路20控制，使得当栅极端子 2相对于源极端子3是正的，开关电路SW3导通，当栅极端子2的电压相对于源极端子3的电压为负时，开关电路SW2导通，并且当 栅极端子2和源极端子3具有几乎相同的电位，并且漏极端子1具有高电位，开关电路SW2导通。通过添加这种控制电路，绝缘栅极半导体装置h 其中根据本发明的保护电路可以减小当向栅极施加负电压时能够从漏极端子流到栅极端子的漏电流，并且可以在不引起漏极击穿电压下降的情况下高速工作。

公开(公告)号：US6057998A

公开(公告)日：2000-05-02

申请号：US998644

申请日：1997-12-29

申请人： Kozo Sakamoto ,  Isao Yoshida

发明人： Kozo Sakamoto ,  Isao Yoshida

IPC分类号： H03K17/08 ,  H03K17/082 ,  H02H3/00

CPC分类号： H03K17/0828 ,  H03K17/0822 ,  H03K2017/0806

摘要： There is disclosed a semiconductor apparatus such as a power MOSFET, an IGBT, or the like having therein a control circuit such as an over-heating protection circuit and an over-current protection circuit, which realizes both of high-speed operation and prevention of erroneous operation caused by a parasitic device.In order to prevent erroneous operation of a power MOSFET 30 and a protection circuit 21 caused by a parasitic npn transistor 29 of an MOSFET 32, a control circuit 20 controls so that when the voltage of a gate terminal 2 is positive relative to that of a source terminal 3, a switch circuit SW3 is turned on, when the voltage of the gate terminal 2 is negative relative to that of the source terminal 3, a switch circuit SW2 is turned on, and when the gate terminal 2 and the source terminal 3 have an almost same potential and a drain terminal 1 has a high potential, the switch circuit SW2 is turned on.By adding such a control circuit, an insulated gate semiconductor apparatus having therein the protection circuit according to the invention can reduce a leakage current flowing from the drain terminal to the gate terminal when a negative voltage is applied to the gate and can operate at high speed without causing drop of a drain breakdown voltage.

摘要翻译： 公开了具有诸如过热保护电路和过电流保护电路等控制电路的功率MOSFET，IGBT等半导体装置，实现了高速运行和防止 由寄生器件引起的错误操作。 为了防止由MOSFET32的寄生npn晶体管29引起的功率MOSFET 30和保护电路21的错误操作，控制电路20控制，使得当栅极端子2的电压相对于 源极端子3，开关电路SW3导通，当栅极端子2的电压相对于源极端子3的电压为负时，开关电路SW2导通，并且当栅极端子2和源极端子3 具有几乎相同的电位，并且漏极端子1具有高电位，开关电路SW2导通。 通过添加这样的控制电路，其中具有根据本发明的保护电路的绝缘栅半导体装置可以减小当向栅极施加负电压并且可以高速运行时从漏极端子流到栅极端子的漏电流 而不会引起漏极击穿电压的下降。

公开(公告)号：US5903034A

公开(公告)日：1999-05-11

申请号：US710009

申请日：1996-09-11

申请人： Kozo Sakamoto ,  Isao Yoshida

发明人： Kozo Sakamoto ,  Isao Yoshida

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/0251 ,  H01L27/0629

摘要： In a semiconductor circuit device having a substrate, a first region of a first conductivity type formed in the substrate, a second region of a second conductivity type contacted to the first region and a MISFET formed in the second region, there is a problem of that a parasitic npn bipolar transistor constituted by the first region, the second region and a source or drain of the MISFET activates. In this invention, switching circuitry is provided to make the second region floating or to connect the second region with the source or drain of the MISFET when a negative first input voltage is input to a source or a drain of the first MISFET. By virtue of the switching circuitry, no base current of the parasitic bipolar transistor occurs, thereby preventing operation of the parasitic transistor. In particular, when the switching circuitry operates to cause the second region to float, the base of the parasitic bipolar transistor will float, and the bipolar transistor cannot operate. Alternatively, when the switching circuitry connects the second region with the source or drain, the base-emitter junction of the parasitic bipolar transistor will be shorted, which also prevents its operation.

摘要翻译： 在具有衬底的半导体电路器件中，形成在衬底中的第一导电类型的第一区域，与第一区域接触的第二导电类型的第二区域和形成在第二区域中的MISFET，存在这样的问题： 由MISFET的第一区域，第二区域和源极或漏极构成的寄生npn双极晶体管激活。 在本发明中，当负的第一输入电压输入到第一MISFET的源极或漏极时，提供开关电路以使第二区域浮置或者将第二区域与MISFET的源极或漏极连接。 由于开关电路，不会发生寄生双极晶体管的基极电流，从而防止寄生晶体管的工作。 特别地，当开关电路操作以使第二区域浮动时，寄生双极晶体管的基极将浮置，并且双极晶体管不能工作。 或者，当开关电路将第二区域与源极或漏极连接时，寄生双极晶体管的基极 - 发射极结将被短路，这也阻止其工作。

公开(公告)号：US20070215903A1

公开(公告)日：2007-09-20

申请号：US11685802

申请日：2007-03-14

申请人： Kozo Sakamoto ,  Toshiaki Ishii

发明人： Kozo Sakamoto ,  Toshiaki Ishii

IPC分类号： H01L31/00

CPC分类号： H01L25/072 ,  H01L23/49844 ,  H01L23/5383 ,  H01L23/5385 ,  H01L25/115 ,  H01L25/117 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599

摘要： A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.

摘要翻译： 一种功率半导体器件，具有第一半导体区域和第二半导体区域; 安装在第一半导体区域中的由第三半导体区域包围的半导体衬底主表面上的第一电极焊盘和具有第一和第二布线层的多层衬底，以取出半导体芯片的电极; 通过导电材料将安装在多层基板上的第一电极的第一布线层部分与由第三半导体区域包围的内部的半导体基板主表面相对的区域和第一电极焊盘接合; 将第一电极的第一布线层部分和导电部分的第二布线层接合; 并且在由所述第三半导体区域包围的内部将所述第二布线层延伸到与所述半导体基板主表面相对的区域的外部。

公开(公告)号：US07005834B2

公开(公告)日：2006-02-28

申请号：US10882672

申请日：2004-07-02

申请人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

发明人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

IPC分类号： G05F1/613 ,  G05F1/656

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： In a power supply of a synchronous rectification type, the self-turn on phenomenon of MOSFET is suppressed without increase of the drive loss to thereby improve the power efficiency. In a synchronous rectifier circuit, a threshold value of a commutation MOSFET is made higher than that of a rectification MOSFET and particularly a threshold value of a commutation MOSFET 3 is made 0.5V or more higher than that of a rectification MOSFET 2. The threshold value of the rectification MOSFET 2 is lower than 1.5V and the threshold of the commutation MOSFET 3 is higher than 2.0V.

摘要翻译： 在同步整流型的电源中，不增加驱动损耗来抑制MOSFET的自转导通现象，从而提高功率效率。 在同步整流电路中，使换向MOSFET的阈值高于整流MOSFET的阈值，特别是使换向MOSFET 3的阈值比整流MOSFET2的阈值高0.5V以上。 整流用MOSFET2的阈值低于1.5V，换流用MOSFET3的阈值高于2.0V。

公开(公告)号：US20050007078A1

公开(公告)日：2005-01-13

申请号：US10882672

申请日：2004-07-02

申请人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

发明人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

IPC分类号： H02M7/21 ,  H02M3/155 ,  H02M3/158 ,  G05F1/652

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： In a power supply of a synchronous rectification type, the self-turn on phenomenon of MOSFET is suppressed without increase of the drive loss to thereby improve the power efficiency. In a synchronous rectifier circuit, a threshold value of a commutation MOSFET is made higher than that of a rectification MOSFET and particularly a threshold value of a commutation MOSFET 3 is made 0.5V or more higher than that of a rectification MOSFET 2. The threshold value of the rectification MOSFET 2 is lower than 1.5V and the threshold of the commutation MOSFET 3 is higher than 2.0V.

摘要翻译： 在同步整流型的电源中，不增加驱动损耗来抑制MOSFET的自转导通现象，从而提高功率效率。 在同步整流电路中，使换向MOSFET的阈值高于整流MOSFET的阈值，特别是使换向MOSFET 3的阈值比整流MOSFET2的阈值高0.5V以上。阈值 的整流用MOSFET2的电压低于1.5V，换流用MOSFET3的阈值高于2.0V。