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    Compounded power MOSFET
    1.
    发明授权
    Compounded power MOSFET 失效
    复合功率MOSFET

    公开(公告)号：US5629542A

    公开(公告)日：1997-05-13

    申请号：US571766

    申请日：1995-12-13

    申请人： Kozo Sakamoto ,  Shigeo Otaka ,  Kyouichi Takagawa

    发明人： Kozo Sakamoto ,  Shigeo Otaka ,  Kyouichi Takagawa

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/06 ,  H03K17/082 ,  H03K19/003 ,  H03K19/0944 ,  H03K19/173 ,  H01L27/02

    CPC分类号： H03K17/0822 ,  H01L27/0629 ,  H01L2924/0002

    摘要： Provided is a compounded power MOSFET which has a high positive and negative withstand voltages for the drain terminal relative to the source terminal, and can be formed on a single chip based on the conventional fabrication process of power MOSFETs. Power MOSFETs 10 and 11 have their drains connected together, the MOSFET 10 has its source and gate used for the source terminal 0 and gate terminal 1, respectively, of the compounded power MOSFET 60, and the MOSFET 11 has its source used for the drain terminal 2. The compounded power MOSFET includes a voltage comparator 50 which drives the MOSFET 11 to turn off when the terminal 2 has a negative voltage, and a voltage transmitter 51 which is connected between the terminal 1 and the gate of the MOSFET 11 to block a current flowing from the terminal 2 to the terminal 1 by way of the circuit 50 and transfer the voltage of the terminal 1 to the gate of the MOSFET 11. The positive withstand voltage is provided by the MOSFET 10, and the negative withstand voltage is provided by the MOSFET 11.

    摘要翻译： 提供了一种复合功率MOSFET，其具有用于漏极端子相对于源极端子的高的正和负的耐受电压，并且可以基于功率MOSFET的常规制造工艺在单个芯片上形成。 功率MOSFET 10和11的漏极连接在一起，MOSFET 10的源极和栅极分别用于复合功率MOSFET 60的源极端子0和栅极端子1，并且MOSFET 11的源极用于漏极 复合功率MOSFET包括电压比较器50，其在端子2具有负电压时驱动MOSFET 11截止;以及电压发射器51，其连接在端子1和MOSFET 11的栅极之间以阻塞 通过电路50从端子2流到端子1的电流，并将端子1的电压传递到MOSFET 11的栅极。正极耐受电压由MOSFET10提供，负的耐压是 由MOSFET 11提供。

    Insulated gate semiconductor device and driving circuit device and electronic system both using the same
    4.
    发明授权
    Insulated gate semiconductor device and driving circuit device and electronic system both using the same 失效
    绝缘栅半导体器件和驱动电路器件和电子系统均采用相同的方式

    公开(公告)号：US5642252A

    公开(公告)日：1997-06-24

    申请号：US288729

    申请日：1994-08-15

    申请人： Kozo Sakamoto ,  Isao Yoshida ,  Shigeo Otaka ,  Tetsuo Iijima ,  Harutora Shono ,  Ken Uchid ,  Masayoshi Kobayashi ,  Hideki Tsunoda

    发明人： Kozo Sakamoto ,  Isao Yoshida ,  Shigeo Otaka ,  Tetsuo Iijima ,  Harutora Shono ,  Ken Uchid ,  Masayoshi Kobayashi ,  Hideki Tsunoda

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/78 ,  H02H5/04 ,  H03K17/08 ,  H03K17/082 ,  H02H3/00

    CPC分类号： H03K17/0822 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/7803 ,  H01L29/7804 ,  H02H5/044 ,  H01L29/0696 ,  H03K2017/0806

    摘要： An improvement in conditions that protective functions of an insulated gate semiconductor device with a protection circuit incorporated therein are performed, an improvement in the cutoff of heating, the prevention of malfunctions and an improvement in ease of usage can be achieved.The insulated gate semiconductor device of the present invention comprises a power insulated gate semiconductor element (M9), at least one MOSFET (M1 through M7) for a protection circuit, for controlling the power insulated gate semiconductor element, a constant-voltage circuit using forward voltages developed across diodes (D2a through D2f) for the constant-voltage circuit, and voltage restricting diodes (D1 and D0a through D0d) for controlling the upper limit of a power supply voltage of the constant-voltage circuit. Power to be supplied to the voltage restricting diodes is supplied from an external gate terminal of the power insulated gate semiconductor element.The present invention can bring about an advantageous effect that an improvement in reliability of the insulated gate semiconductor device and an improvement in the ease of use can be achieved.

    摘要翻译： 可以实现具有并入其中的保护电路的绝缘栅半导体器件的保护功能的条件的改善，可以提高加热截止，防止故障和提高易用性。 本发明的绝缘栅半导体器件包括功率绝缘栅极半导体元件（M9），用于保护电路的至少一个MOSFET（M1至M7），用于控制功率绝缘栅极半导体元件，使用正向的恒压电路 用于恒压电路的二极管（D2a至D2f）上产生的电压以及用于控制恒压电路的电源电压的上限的电压限制二极管（D1和D0a至D0d）。 供电到限压二极管的功率从功率绝缘栅极半导体元件的外部栅极端子提供。 本发明可以实现提高绝缘栅极半导体器件的可靠性和提高易用性的有利效果。

    POWER SEMICONDUCTOR DEVICE
    5.
    发明申请
    POWER SEMICONDUCTOR DEVICE 有权
    功率半导体器件

    公开(公告)号：US20070215903A1

    公开(公告)日：2007-09-20

    申请号：US11685802

    申请日：2007-03-14

    申请人： Kozo Sakamoto ,  Toshiaki Ishii

    发明人： Kozo Sakamoto ,  Toshiaki Ishii

    IPC分类号： H01L31/00

    CPC分类号： H01L25/072 ,  H01L23/49844 ,  H01L23/5383 ,  H01L23/5385 ,  H01L25/115 ,  H01L25/117 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599

    摘要： A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.

    摘要翻译： 一种功率半导体器件，具有第一半导体区域和第二半导体区域; 安装在第一半导体区域中的由第三半导体区域包围的半导体衬底主表面上的第一电极焊盘和具有第一和第二布线层的多层衬底，以取出半导体芯片的电极; 通过导电材料将安装在多层基板上的第一电极的第一布线层部分与由第三半导体区域包围的内部的半导体基板主表面相对的区域和第一电极焊盘接合; 将第一电极的第一布线层部分和导电部分的第二布线层接合; 并且在由所述第三半导体区域包围的内部将所述第二布线层延伸到与所述半导体基板主表面相对的区域的外部。

    Synchronous rectifier circuit and power supply
    6.
    发明授权
    Synchronous rectifier circuit and power supply 有权
    同步整流电路和电源

    公开(公告)号：US07005834B2

    公开(公告)日：2006-02-28

    申请号：US10882672

    申请日：2004-07-02

    申请人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

    发明人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

    IPC分类号： G05F1/613 ,  G05F1/656

    CPC分类号： H02M3/1588 ,  Y02B70/1466

    摘要： In a power supply of a synchronous rectification type, the self-turn on phenomenon of MOSFET is suppressed without increase of the drive loss to thereby improve the power efficiency. In a synchronous rectifier circuit, a threshold value of a commutation MOSFET is made higher than that of a rectification MOSFET and particularly a threshold value of a commutation MOSFET 3 is made 0.5V or more higher than that of a rectification MOSFET 2. The threshold value of the rectification MOSFET 2 is lower than 1.5V and the threshold of the commutation MOSFET 3 is higher than 2.0V.

    摘要翻译： 在同步整流型的电源中，不增加驱动损耗来抑制MOSFET的自转导通现象，从而提高功率效率。 在同步整流电路中，使换向MOSFET的阈值高于整流MOSFET的阈值，特别是使换向MOSFET 3的阈值比整流MOSFET2的阈值高0.5V以上。 整流用MOSFET2的阈值低于1.5V，换流用MOSFET3的阈值高于2.0V。

    Synchronous rectifier circuit and power supply
    7.
    发明申请
    Synchronous rectifier circuit and power supply 有权
    同步整流电路和电源

    公开(公告)号：US20050007078A1

    公开(公告)日：2005-01-13

    申请号：US10882672

    申请日：2004-07-02

    申请人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

    发明人： Takayuki Iwasaki ,  Kozo Sakamoto ,  Masaki Shiraishi ,  Nobuyoshi Matsuura ,  Tomoaki Uno

    IPC分类号： H02M7/21 ,  H02M3/155 ,  H02M3/158 ,  G05F1/652

    CPC分类号： H02M3/1588 ,  Y02B70/1466

    摘要： In a power supply of a synchronous rectification type, the self-turn on phenomenon of MOSFET is suppressed without increase of the drive loss to thereby improve the power efficiency. In a synchronous rectifier circuit, a threshold value of a commutation MOSFET is made higher than that of a rectification MOSFET and particularly a threshold value of a commutation MOSFET 3 is made 0.5V or more higher than that of a rectification MOSFET 2. The threshold value of the rectification MOSFET 2 is lower than 1.5V and the threshold of the commutation MOSFET 3 is higher than 2.0V.

    摘要翻译： 在同步整流型的电源中，不增加驱动损耗来抑制MOSFET的自转导通现象，从而提高功率效率。 在同步整流电路中，使换向MOSFET的阈值高于整流MOSFET的阈值，特别是使换向MOSFET 3的阈值比整流MOSFET2的阈值高0.5V以上。阈值 的整流用MOSFET2的电压低于1.5V，换流用MOSFET3的阈值高于2.0V。

    POWER SEMICONDUCTOR DEVICE
    8.
    发明申请
    POWER SEMICONDUCTOR DEVICE 有权
    功率半导体器件

    公开(公告)号：US20090179321A1

    公开(公告)日：2009-07-16

    申请号：US12407041

    申请日：2009-03-19

    申请人： Kozo Sakamoto ,  Toshiaki Ishii

    发明人： Kozo Sakamoto ,  Toshiaki Ishii

    IPC分类号： H01L23/12

    CPC分类号： H01L25/072 ,  H01L23/49844 ,  H01L23/5383 ,  H01L23/5385 ,  H01L25/115 ,  H01L25/117 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599

    摘要： A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.

    摘要翻译： 一种功率半导体器件，具有第一半导体区域和第二半导体区域; 安装在第一半导体区域中的由第三半导体区域包围的半导体衬底主表面上的第一电极焊盘和具有第一和第二布线层的多层衬底，以取出半导体芯片的电极; 通过导电材料将安装在多层基板上的第一电极的第一布线层部分与由第三半导体区域包围的内部的半导体基板主表面相对的区域和第一电极焊盘接合; 将第一电极的第一布线层部分和导电部分的第二布线层接合; 并且在由所述第三半导体区域包围的内部将所述第二布线层延伸到与所述半导体基板主表面相对的区域的外部。

    SEMICONDUCTOR CIRCUIT
    9.
    发明申请
    SEMICONDUCTOR CIRCUIT 有权
    半导体电路

    公开(公告)号：US20080205100A1

    公开(公告)日：2008-08-28

    申请号：US12028364

    申请日：2008-02-08

    申请人： Kozo Sakamoto

    发明人： Kozo Sakamoto

    IPC分类号： H02M7/06

    CPC分类号： H03K17/6871 ,  H02M3/07 ,  H02M3/1588 ,  H02M2003/1555 ,  H03K17/165 ,  H03K17/691 ,  H03K17/785 ,  H03K2017/6875 ,  H03K2217/0036 ,  Y02B70/1466

    摘要： A synchronous rectifying drive type semiconductor circuit wherein voltages between drains and sources of power switching elements are detected, temporarily held and compared with a reference voltage. First control signals are generated for turning on the power switching elements depending on comparison result and dead times for the power switching elements are minimized by ORing first control signals and second control signals inputted at input terminals. The first control signals cause the power switching elements to be in “on” state for a constant time until the second control signals as “on” control signals arrive at the input terminals, and then the first control signals as “on” control signals are terminated before the second control signals as “off” signals arrive at the input terminals, thereby swiftly turning off the power switching elements by the second control signals arriving at the input terminals.

    摘要翻译： 同时整流驱动型半导体电路，其中检漏电源开关元件的漏极和电源之间的电压，暂时保持并与参考电压进行比较。 产生用于根据比较结果接通功率开关元件的第一控制信号，并且通过对在输入端输入的第一控制信号和第二控制信号进行或运算来最小化功率开关元件的死区时间。 第一控制信号使功率开关元件处于“接通”状态一直到第二控制信号为“接通”控制信号到达输入端，然后第一控制信号为“接通”控制信号 在第二控制信号作为“关闭”信号到达输入端之前终止，从而通过到达输入端的第二控制信号迅速关闭功率开关元件。

    Semiconductor circuit
    10.
    发明授权
    Semiconductor circuit 有权
    半导体电路

    公开(公告)号：US07952339B2

    公开(公告)日：2011-05-31

    申请号：US12028364

    申请日：2008-02-08

    申请人： Kozo Sakamoto

    发明人： Kozo Sakamoto

    IPC分类号： G05F1/575 ,  G05F1/618

    CPC分类号： H03K17/6871 ,  H02M3/07 ,  H02M3/1588 ,  H02M2003/1555 ,  H03K17/165 ,  H03K17/691 ,  H03K17/785 ,  H03K2017/6875 ,  H03K2217/0036 ,  Y02B70/1466

    摘要： A synchronous rectifying drive type semiconductor circuit wherein voltages between drains and sources of power switching elements are detected, temporarily held and compared with a reference voltage. First control signals are generated for turning on the power switching elements depending on comparison result and dead times for the power switching elements are minimized by ORing first control signals and second control signals inputted at input terminals. The first control signals cause the power switching elements to be in “on” state for a constant time until the second control signals as “on” control signals arrive at the input terminals, and then the first control signals as “on” control signals are terminated before the second control signals as “off” signals arrive at the input terminals, thereby swiftly turning off the power switching elements by the second control signals arriving at the input terminals.

    摘要翻译： 同时整流驱动型半导体电路，其中检漏电源开关元件的漏极和电源之间的电压，暂时保持并与参考电压进行比较。 产生用于根据比较结果接通功率开关元件的第一控制信号，并且通过对在输入端输入的第一控制信号和第二控制信号进行或运算来最小化功率开关元件的死区时间。 第一控制信号使功率开关元件处于“接通”状态一直到第二控制信号为“接通”控制信号到达输入端，然后第一控制信号为“接通”控制信号 在第二控制信号作为“关闭”信号到达输入端之前终止，从而通过到达输入端的第二控制信号迅速关闭功率开关元件。