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    Method and apparatus for producing a manganese-zinc ferrite single crystal using a local liquid pool formation
    1.
    发明授权
    Method and apparatus for producing a manganese-zinc ferrite single crystal using a local liquid pool formation 失效
    使用局部液池形成生产锰锌铁氧体单晶的方法和装置

    公开(公告)号：US5268061A

    公开(公告)日：1993-12-07

    申请号：US950214

    申请日：1992-09-24

    申请人： Kuk H. Sunwoo ,  Jae Y. Ma ,  Tae H. Kim

    发明人： Kuk H. Sunwoo ,  Jae Y. Ma ,  Tae H. Kim

    IPC分类号： C30B15/24 ,  C30B15/00 ,  C30B15/34 ,  C30B29/22 ,  C30B15/22

    CPC分类号： C30B15/34 ,  C30B15/00 ,  C30B29/24 ,  Y10T117/1008 ,  Y10T117/1036 ,  Y10T117/1068

    摘要： A method and apparatus for producing a manganese-zinc ferrite single crystal using a local liquid pool formation which involves melting of a starting material in a crucible and lowering of the temperature of crucible to make the resultant melt maintain form three phase regions of an upper liquid pool region, an intermediate semi-rigid region and a lower solid region. A pair of heaters are disposed at the upper and side wall portions of crucible and controlled differently from each other so that the formed lower solid region extends at its peripheral portion throughout the inner surface of the side wall portion of the crucible, thereby minimizing the contact of the formed upper liquid pool region with the whole inner surface of the crucible. For monitoring respective temperatures of various portions in the crucible to control the heaters, there are provided thermocouples which includes a thermocouple for the crystal drawing port member, a thermocouple for the upper portion of crucible, a thermocouple for the upper portion of the side wall of crucible and a thermocouple for the lower portion of crucible.

    摘要翻译： 一种使用局部液体池形成生产锰锌铁氧体单晶的方法和装置，其包括在坩埚中熔化原料并降低坩埚的温度以使所得熔体保持形成上部液体的三相区域 池区域，中间半刚性区域和下部固体区域。 一对加热器设置在坩埚的上壁部分和侧壁部分，并且彼此不同地控制，使得形成的下部固体区域在其周边部分延伸贯穿坩埚的侧壁部分的内表面，从而使接触最小化 形成的上部液体池区域与坩埚的整个内表面。 为了监测坩埚中各部分的温度以控制加热器，提供了热电偶，其包括用于晶体抽出口部件的热电偶，用于坩埚上部的热电偶，用于上部侧壁的热电偶 坩埚和用于坩埚下部的热电偶。

    Timing analysis of an array circuit cross section
    3.
    发明授权
    Timing analysis of an array circuit cross section 失效
    阵列电路截面的时序分析

    公开(公告)号：US08495537B1

    公开(公告)日：2013-07-23

    申请号：US13349325

    申请日：2012-01-12

    申请人： Shyamkumar Thoziyoor ,  Tae H. Kim ,  Sang Y. Lee

    发明人： Shyamkumar Thoziyoor ,  Tae H. Kim ,  Sang Y. Lee

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： A method, system or computer usable program product for performing timing analysis on an array circuit including receiving in memory a set of pins to be timed, selecting with a data processor a cross section of the array circuit including the set of pins wherein a backtrace is performed from the set of pins to identify a set of bus groups, each bus group having a plurality of timing pins, and assigning timing for an assigned pin of a first bus group equal to timing calculated for a surrogate pin of the first bus group based on array circuit regularity.

    摘要翻译： 一种用于对阵列电路进行定时分析的方法，系统或计算机可用程序产品，包括在存储器中接收要定时的一组引脚，用数据处理器选择包括该组引脚的阵列电路的横截面，其中回溯是 从所述一组引脚执行以识别一组总线组，每个总线组具有多个定时引脚，以及为第一总线组的分配引脚分配等于基于第一总线组的替代引脚的定时的定时 阵列电路规律性。

    Printed Circuit Board With Reduced Signal Distortion
    4.
    发明申请
    Printed Circuit Board With Reduced Signal Distortion 有权
    具有减少信号失真的印刷电路板

    公开(公告)号：US20090308649A1

    公开(公告)日：2009-12-17

    申请号：US12140730

    申请日：2008-06-17

    申请人： Moises Cases ,  Tae H. Kim ,  Bhyrav M. Mutnury

    发明人： Moises Cases ,  Tae H. Kim ,  Bhyrav M. Mutnury

    IPC分类号： H05K1/11 ,  H05K3/00 ,  G06F17/50

    CPC分类号： H05K1/0224 ,  H05K1/0225 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/0005 ,  H05K2201/09681 ,  Y10T29/49124

    摘要： A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.

    摘要翻译： 具有降低的信号失真的印刷电路板，包括一层或多层不导电基底，在其上设置传导信号的导电路径，其特征在于至少部分地由印刷的层上的导电路径的取向引起的变形 电路板和周期性图案化参考平面; 每个导电通路相对于在印刷电路板上传导信号的其它导电通路传导正交或对角地定向四十五度的信号; 所述周期性图案化参考平面包括具有以周期性重复图案布置的不连续性的导体，所述不连续性的图案相对于在所述印刷电路板上传导信号的导电路径以最佳角度定向在所述印刷电路板的层的表面上 印刷电路板，可以减少信号的失真。

    Level shifter for low voltage operation
    5.
    发明授权
    Level shifter for low voltage operation 有权
    电平移位器用于低电压工作

    公开(公告)号：US07200053B2

    公开(公告)日：2007-04-03

    申请号：US10931587

    申请日：2004-09-01

    申请人： Tae H. Kim ,  Michael V. Cordoba ,  Howard C. Kirsch

    发明人： Tae H. Kim ,  Michael V. Cordoba ,  Howard C. Kirsch

    IPC分类号： G11C7/00

    CPC分类号： G11C5/147 ,  G11C16/30 ,  H03K3/356113

    摘要： A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.

    摘要翻译： 电压电平转换器提高晶体管的栅极电压，并增加栅极到源极电压，以允许在更宽的电源电压范围内工作。 因此，电压电平转换器中的晶体管的P / N比被增加，并且节点的翻转的控制取决于栅极电压而不是P / N比。

    Method for fabricating a magnetic head
    6.
    发明授权
    Method for fabricating a magnetic head 失效
    磁头制造方法

    公开(公告)号：US5503696A

    公开(公告)日：1996-04-02

    申请号：US234276

    申请日：1994-04-28

    申请人： Tae H. Kim

    发明人： Tae H. Kim

    IPC分类号： G11B5/127 ,  G11B5/133 ,  G11B5/147 ,  G11B5/187 ,  G11B5/23 ,  G11B5/235

    CPC分类号： G11B5/232 ,  G11B5/1335 ,  G11B5/1878 ,  G11B5/235 ,  Y10T156/1062 ,  Y10T156/1069 ,  Y10T156/1075

    摘要： A method for fabricating a magnetic head includes steps of stacking a magnetic layer on a ceramic substrate, coating an adhesive over the magnetic layer while rotating the substrate in a predetermined speed, forming a substrate block by stacking a plurality of substrates, and forming at least one pair of magnetic ferrite blocks by vertically and longitudinally slicing the substrate block. The adhesive is consistently coated on a gap formation plane of the magnetic ferrite block while being rotated by a predetermined speed, the pair of ferrite blocks are pressed to be bonded to each other, thereby completing the magnetic head.

    摘要翻译： 一种用于制造磁头的方法包括以下步骤：在陶瓷基片上层叠磁性层，同时以预定速度旋转衬底，在磁性层上涂覆粘合剂，通过堆叠多个衬底形成衬底块，至少形成 一对磁性铁氧体块通过垂直和纵向地切割衬底块。 粘合剂一直涂覆在磁性铁氧体块的间隙形成平面上同时以预定的速度旋转，一对铁氧体块被按压以彼此接合，从而完成磁头。

    Tool and Method for Securing a Pocket Square
    8.
    发明申请
    Tool and Method for Securing a Pocket Square 有权

    公开(公告)号：US20210212388A1

    公开(公告)日：2021-07-15

    申请号：US16069786

    申请日：2018-03-15

    申请人： Tae H. Kim

    发明人： Tae H. Kim

    IPC分类号： A41B15/02 ,  A45F5/04

    摘要： A pocket square tool comprises a pliable outer rod in a closed loop, having a substantially straight horizontal top edge and a curved U-shaped bottom edge, and a substantially straight pliable horizontal intermediate rod extending a horizontal distance between a left edge of the outer rod and a right edge of the outer rod and parallel to the top edge of the outer rod. The pocket square tool is adjustable in size. There are two intermediate rods parallel to each other. Other embodiments may have additional intermediate rods. The intermediate rods can be coupled to the outer rod or formed integral to it. Various methods of securing a pocket square use the tool.

    TIMING ANALYSIS OF AN ARRAY CIRCUIT CROSS SECTION
    9.
    发明申请
    TIMING ANALYSIS OF AN ARRAY CIRCUIT CROSS SECTION 失效
    阵列电路交叉部分的时序分析

    公开(公告)号：US20130185685A1

    公开(公告)日：2013-07-18

    申请号：US13349325

    申请日：2012-01-12

    申请人： Shyamkumar Thoziyoor ,  Tae H. Kim ,  Sang Y. Lee

    发明人： Shyamkumar Thoziyoor ,  Tae H. Kim ,  Sang Y. Lee

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： A method, system or computer usable program product for performing timing analysis on an array circuit including receiving in memory a set of pins to be timed, selecting with a data processor a cross section of the array circuit including the set of pins wherein a backtrace is performed from the set of pins to identify a set of bus groups, each bus group having a plurality of timing pins, and assigning timing for an assigned pin of a first bus group equal to timing calculated for a surrogate pin of the first bus group based on array circuit regularity.

    摘要翻译： 一种用于对阵列电路进行定时分析的方法，系统或计算机可用程序产品，包括在存储器中接收要定时的一组引脚，用数据处理器选择包括所述一组引脚的阵列电路的横截面，其中回溯是 从所述一组引脚执行以识别一组总线组，每个总线组具有多个定时引脚，以及为第一总线组的分配引脚分配等于基于第一总线组的替代引脚的定时的定时 阵列电路规律性。