Method and apparatus for inspecting the surface of a semiconductor device
    1.
    发明授权
    Method and apparatus for inspecting the surface of a semiconductor device 有权
    用于检查半导体器件表面的方法和装置

    公开(公告)号:US06507394B1

    公开(公告)日:2003-01-14

    申请号:US09449884

    申请日:1999-11-30

    IPC分类号: G01N2100

    CPC分类号: G01N21/9501

    摘要: An optical inspection system for detecting defects on the surface of a semiconductor wafer includes two light sources and two light receivers mounted as a common assembly which is rotated such that two curtains of light and corresponding linear photosensor arrays circularly scan the wafer surface. The reflected light is analyzed to determine the presence of surface defects. Marks applied to the wafer surface provide amplitude and timing references used to adjust and synchronize the analyzed signals.

    摘要翻译: 用于检测半导体晶片表面上的缺陷的光学检查系统包括两个光源和两个光接收器,其安装为共同组件,其被旋转使得两个窗帘和相应的线性光电传感器阵列循环扫描晶片表面。 分析反射光以确定表面缺陷的存在。 施加到晶片表面的标记提供用于调整和同步分析的信号的幅度和定时参考。

    Overlay registration correction method for multiple product type microelectronic fabrication foundry facility
    5.
    发明授权
    Overlay registration correction method for multiple product type microelectronic fabrication foundry facility 失效
    多重产品型微电子制造代工厂的覆盖注册修正方法

    公开(公告)号:US06735485B1

    公开(公告)日:2004-05-11

    申请号:US10290925

    申请日:2002-11-08

    IPC分类号: G05B1900

    摘要: A method for determining an overlay registration correction for a new product lot of a microelectronic product type with respect to a specific alignment tool within a foundry facility first provides for determining: (1) a first average historic overlay registration correction for historic product lots of the new product lot type with respect to the specific alignment tool; and (2) a second average historic overlay registration correction with respect to product lots of any product type with respect to the specific alignment tool. The overlay registration correction is determined as the sum of: (1) an overlay registration correction for an immediately preceding layer within the new product lot, if present; (2) a factor derived from the first average historic overlay registration correction; and (3) a factor derived from the second average historic overlay registration correction.

    摘要翻译: 用于确定关于铸造设备中的特定对准工具的微电子产品类型的新产品批次的重叠注册校正的方法首先确定:(1)针对历史产品批次的第一平均历史重叠注册校正 新产品批次类型相对于具体的对齐工具; 和(2)相对于特定对准工具的任何产品类型的产品批次的第二平均历史重叠登记修正。 确定覆盖登记修正为:(1)如果存在新产品批次中的紧邻前一层的叠加登记修正; (2)从第一次平均历史重叠登记纠正得出的因子; 和(3)来自第二平均历史重叠登记修正的因子。

    Smart overlay control
    7.
    发明申请
    Smart overlay control 失效
    智能覆盖控制

    公开(公告)号:US20050071033A1

    公开(公告)日:2005-03-31

    申请号:US10672394

    申请日:2003-09-26

    IPC分类号: G06F19/00

    CPC分类号: G03F7/70633 G03F7/70525

    摘要: An automatic method to maintain and correct overlay in the fabrication of integrated circuits is described. An overlay control table is automatically generated for lots run through a process tool. An overlay correction is calculated from the overlay control table and sent to the process tool for real-time or manual overlay correction.

    摘要翻译: 描述了在集成电路的制造中维护和校正覆盖的自动方法。 自动生成覆盖控制表,用于批处理工具。 从覆盖控制表计算覆盖校正,并发送到过程工具进行实时或手动叠加校正。

    Smart overlay control
    8.
    发明授权
    Smart overlay control 失效
    智能覆盖控制

    公开(公告)号:US07031794B2

    公开(公告)日:2006-04-18

    申请号:US10672394

    申请日:2003-09-26

    IPC分类号: G06F19/00

    CPC分类号: G03F7/70633 G03F7/70525

    摘要: An automatic method to maintain and correct overlay in the fabrication of integrated circuits is described. An overlay control table is automatically generated for lots run through a process tool. An overlay correction is calculated from the overlay control table and sent to the process tool for real-time or manual overlay correction.

    摘要翻译: 描述了在集成电路的制造中维护和校正覆盖的自动方法。 自动生成覆盖控制表,用于批处理工具。 从覆盖控制表计算覆盖校正,并发送到过程工具进行实时或手动叠加校正。

    Use of sub divided pattern for alignment mark recovery after inter-level
dielectric planarization
    9.
    发明授权
    Use of sub divided pattern for alignment mark recovery after inter-level dielectric planarization 失效
    在层间电介质平坦化之后使用子分割图案进行对准标记恢复

    公开(公告)号:US5843600A

    公开(公告)日:1998-12-01

    申请号:US901168

    申请日:1997-07-28

    IPC分类号: G03F1/00 G03F7/00 G03F9/00

    摘要: A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.

    摘要翻译: 不需要额外的掩模版的掩模,以及在层间电介质层已被平坦化之后使用掩模来恢复晶片中的对准标记的方法,并且第二层金属已沉积在平坦化的层间电介质上 描述层。 对准标记保护图案和清晰窗口图案被细分,使得它们可以由第一和第二掩模元件形成。 这些掩模元件可以形成在用于对晶片的器件区域进行图案化的掩模版的周边区域中。 掩模元件用于在光致抗蚀剂的第一层中曝光对准标记保护图案,并在第二层光致抗蚀剂中露出清漆窗口图案。