利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.038 秒)

    Process for providing clean lift-off of sputtered thin film layers
    1.
    发明授权
    Process for providing clean lift-off of sputtered thin film layers 失效
    提供溅射薄膜层清洁剥离的工艺

    公开(公告)号：US5705432A

    公开(公告)日：1998-01-06

    申请号：US566197

    申请日：1995-12-01

    申请人： Kusol Lee ,  Tom Quach ,  Danny Li ,  Liping D. Hou ,  Sam Chung ,  Tom Y. Chi

    发明人： Kusol Lee ,  Tom Quach ,  Danny Li ,  Liping D. Hou ,  Sam Chung ,  Tom Y. Chi

    IPC分类号： H01L21/027 ,  H01L21/465

    CPC分类号： H01L21/0272 ,  Y10S438/951

    摘要： A unique photoresist process is provided which achieves clean and complete lift-off of a thin film layer such as a sputtered thin film formed on a photoresist which is formed above a semiconductor substrate. The process of the present invention relies on a reentrant photoresist profile which breaks the continuity of the thin film layer. Accordingly, the process of the present invention ensures a clean lift-off. The desired photoresist profile which breaks the continuity of the thin film layer can be obtained by a typical photoresist process preceded by an oxidation process that takes place on the surface of the semiconductor substrate. The oxidation process provides a thin native oxide layer with thickness ranging from about 30 to 50 .ANG.. No extra processing steps involving dielectric film deposition and etch are required to achieve clean lift-off. Nevertheless, the process of the present invention ensures the clean lift-off of the thin film layer. Accordingly, the process of the present invention provides good visual and electrical yields.

    摘要翻译： 提供了一种独特的光刻胶工艺，其实现了清洁和完全剥离薄膜层，例如形成在半导体衬底上的光致抗蚀剂上形成的溅射薄膜。 本发明的方法依赖于破坏薄膜层的连续性的可重入光致抗蚀剂轮廓。 因此，本发明的方法确保了清洁的剥离。 可以通过在半导体衬底的表面上发生的氧化工艺之前的典型的光致抗蚀剂工艺来获得破坏薄膜层的连续性的期望的光致抗蚀剂轮廓。 氧化过程提供厚度范围为约30至50安培的薄的天然氧化物层。 不需要涉及介电膜沉积和蚀刻的额外处理步骤来实现干净的剥离。 然而，本发明的方法确保了薄膜层的清洁剥离。 因此，本发明的方法提供良好的视觉和电产量。

    Method of fabricating a self-aligned double recess gate profile
    2.
    发明授权
    Method of fabricating a self-aligned double recess gate profile 失效
    制造自对准双凹槽浇口型材的方法

    公开(公告)号：US5556797A

    公开(公告)日：1996-09-17

    申请号：US453676

    申请日：1995-05-30

    申请人： Tom Y. Chi ,  Liping D. Hou ,  Kusol Lee ,  Danny Li ,  Ishver K. Naik ,  Tom Quach

    发明人： Tom Y. Chi ,  Liping D. Hou ,  Kusol Lee ,  Danny Li ,  Ishver K. Naik ,  Tom Quach

    IPC分类号： H01L21/338 ,  H01L29/812 ,  H01L21/8258

    CPC分类号： H01L29/66871 ,  H01L29/8128

    摘要： A method of fabricating a self-aligned double gate recess profile in a semiconductor substrate is disclosed in which a first mask layer is formed over the substrate. A second mask layer having an opening is formed over the first mask layer. An opening at least as wide as the second mask layer's opening is formed through the first mask layer to expose the substrate beneath the second mask layer's opening. A first recess is etched in the semiconductor through the second mask layer's opening. The first mask layer's opening is then uniformly expanded and a wider recess, aligned to the first recess, is then formed in the semiconductor. The method is particularly applicable to the formation of self-aligned gate and channel recesses in a GaAs MESFET.

    摘要翻译： 公开了一种在半导体衬底中制造自对准双栅凹槽轮廓的方法，其中在衬底上形成第一掩模层。 在第一掩模层上形成具有开口的第二掩模层。 通过第一掩模层形成至少与第二掩模层开口一样宽的开口，以将第二掩模层开口下方的基板曝光。 通过第二掩模层的开口在半导体中蚀刻第一凹槽。 然后将第一掩模层的开口均匀地膨胀，然后在半导体中形成与第一凹部对准的更宽的凹部。 该方法特别适用于GaAs MESFET中自对准栅极和沟槽的形成。

    Dual etchant process, particularly for gate recess fabrication in GaAs MMIC chips
    3.
    发明授权
    Dual etchant process, particularly for gate recess fabrication in GaAs MMIC chips 失效
    双蚀刻工艺，特别适用于GaAs MMIC芯片中的栅极凹槽制造

    公开(公告)号：US5436201A

    公开(公告)日：1995-07-25

    申请号：US68871

    申请日：1993-05-28

    申请人： Tom Y. Chi ,  Danny Li ,  Liping Hou ,  Tom Quach

    发明人： Tom Y. Chi ,  Danny Li ,  Liping Hou ,  Tom Quach

    IPC分类号： H01L21/306 ,  H01L21/338 ,  H01L21/8252

    CPC分类号： H01L29/66863 ,  H01L21/30612

    摘要： A semiconductor substrate is etched in a two-step sequence, with two different liquid etchants that have different lateral etch rates. The relative time periods for which the etchants are applied are selected to achieve a close match between the actual etch profile and the desired profile. The process is particularly applicable to the formation of a gate recess in a GaAs MESFET for high power amplification.

    摘要翻译： 用两步序列蚀刻半导体衬底，使用具有不同横向蚀刻速率的两种不同的液体蚀刻剂。 选择施加蚀刻剂的相对时间段以实现实际蚀刻轮廓和期望轮廓之间的紧密匹配。 该方法特别适用于在用于高功率放大的GaAs MESFET中形成栅极凹槽。

    Distributed cell monolithic mircowave integrated circuit (MMIC) field-effect transistor (FET) amplifier
    5.
    发明授权
    Distributed cell monolithic mircowave integrated circuit (MMIC) field-effect transistor (FET) amplifier 失效
    分布式电池单片微波集成电路（MMIC）场效应晶体管（FET）放大器

    公开(公告)号：US5283452A

    公开(公告)日：1994-02-01

    申请号：US837448

    申请日：1992-02-14

    申请人： Yi-Chi Shih ,  David C. Wang ,  Huy M. Le ,  Vincent Hwang ,  Tom Y. Chi

    发明人： Yi-Chi Shih ,  David C. Wang ,  Huy M. Le ,  Vincent Hwang ,  Tom Y. Chi

    IPC分类号： H01L29/417 ,  H01L29/812

    CPC分类号： H01L29/41758

    摘要： A distributed cell field-effect transistor (FET) amplifier (40) includes a plurality of parallel, elongated source (46a) and drain (46b) regions of individual FET unit cells (46) formed in a substrate (42) in transverse alternating relation, with a plurality of elongated channel regions (46c) being formed between and parallel to adjacent source (46a) and drain (46b) regions respectively. A source foot (48) and a drain foot (50) extend perpendicular to the source (46a) and drain (46b) regions on opposite longitudinally spaced sides thereof respectively. A gate foot (52) extends parallel to the source (48) and drain (50) feet, between the source foot (48) and the cells (46). Source (54) and drain (56) pads and gate (58) fingers extend from the source (48), drain (50) and gate (52) feet into electrical connection with the respective source (46a), drain (46b) and gate ( 46c) regions respectively. The source pads (54) include airbridge portions (54b) which extend over the gate foot (52) without making contact therewith. A fixed tuning circuit (70) is connected between the gate foot (52) and source foot (48), including an inductive stub (72) having a first end connected to the gate foot (52) and a second end, and a capacitor (74) having a first plate (74a) which is integral with the source foot (48) and a second plate connected to the second end of the stub (72). The integration of the capacitor (74) with the source foot (48) enables the amplifier (40) to be tuned at the gate foot (52), thereby eliminating undesirable coupling effects and the need for a separate via for the tuning circuit (70).

    摘要翻译： 分布式单元场效应晶体管（FET）放大器（40）包括以横向交替关系形成在基板（42）中的单个FET单元（46）的多个平行细长源（46a）和漏极（46b） ，其中多个细长沟道区（46c）分别形成在平行于相邻源（46a）和漏极（46b）之间并且平行于漏极（46b）区域。 源脚（48）和排水脚（50）分别垂直于源（46a）和相对的纵向间隔开的排出（46b）区域延伸。 门脚（52）平行于源脚（48）和细胞（46）之间的源极（48）和漏极（50）脚延伸。 源极（54）和漏极（56）焊盘和栅极（58）指状物从源极（48），漏极（50）和栅极（52）脚延伸到与相应源极（46a），漏极（46b）和 门（46c）区域。 源极焊盘（54）包括在栅极（52）上延伸而不与其接触的气桥部分（54b）。 固定调谐电路（70）连接在栅极脚（52）和源脚（48）之间，包括具有连接到栅极脚（52）的第一端和第二端的电感短截线（72），以及电容器 （74）具有与源脚（48）成一体的第一板（74a）和连接到短截线（72）的第二端的第二板。 电容器（74）与源极（48）的集成使得放大器（40）能够在栅极脚（52）处被调谐，从而消除不期望的耦合效应，并且需要用于调谐电路（70）的单独的通孔 ）。

    Field-effect transistor with high breakdown voltage provided by channel recess offset toward drain
    6.
    发明授权
    Field-effect transistor with high breakdown voltage provided by channel recess offset toward drain 失效
    具有高漏电压的场效应晶体管由通道凹槽向漏极偏移提供

    公开(公告)号：US5539228A

    公开(公告)日：1996-07-23

    申请号：US385386

    申请日：1995-02-07

    申请人： Tom Y. Chi

    发明人： Tom Y. Chi

    IPC分类号： H01L21/285 ,  H01L21/338 ,  H01L29/812 ,  H01L29/80 ,  H01L31/112

    CPC分类号： H01L29/66863 ,  H01L21/28587 ,  H01L29/8128

    摘要： A monolithic-microwave-integrated-circuit (MMIC) metal-semiconductor-field-effect (MESFET) transistor (40) or other type of field-effect transistor has a double-recessed channel region (32,42) with a gate recess (42) formed in a channel recess (32). The channel recess (32) is offset toward the drain (16) as far as possible without shorting the channel recess (32) to the drain (16) to increase the transistor breakdown voltage. The gate recess (42) is offset toward the source (14) as far as possible without causing the gate-source capacitance to increase, thereby reducing the transistor source resistance.

    摘要翻译： 单片微波集成电路（MMIC）金属 - 半导体场效应（MICFET）晶体管（40）或其他类型的场效应晶体管具有带凹槽的双凹沟道区域（32,42） 42）形成在通道凹部（32）中。 通道凹部（32）尽可能地朝向漏极（16）偏移，而不会将通道凹槽（32）短路到漏极（16），以增加晶体管击穿电压。 栅极凹部（42）尽可能地朝向源极（14）偏移，而不会使栅极 - 源极电容增加，从而降低晶体管源极电阻。

    Maskless process for forming refractory metal layer in via holes of GaAs chips
    7.
    发明授权
    Maskless process for forming refractory metal layer in via holes of GaAs chips 失效
    在GaAs芯片的通孔中形成难熔金属层的无掩模工艺

    公开(公告)号：US5350662A

    公开(公告)日：1994-09-27

    申请号：US181371

    申请日：1994-01-13

    申请人： Tom Y. Chi

    发明人： Tom Y. Chi

    IPC分类号： G03F7/20 ,  H01L21/027 ,  H01L23/48

    CPC分类号： H01L21/0274 ,  G03F7/2022 ,  H01L23/481 ,  H01L2924/0002

    摘要： A "maskless" process is provided for the formation of a refractory metal layer (22b), such as titanium, in via holes (18) through GaAs wafers (12) to contact microwave monolithic integrated circuit (MMIC) devices (10) formed on the front surface (12a) thereof. The process of the invention, which prevents AuSn solder (28) from filling up the holes during a subsequent eutectic AuSn bonding of the device to a metal carrier (30), such as molybdenum, utilizes the difference of resist thickness on the GaAs backside surface (12b) and in the via holes, so that the resist (24b) remaining in the via holes after removing the resist (24a) over the GaAs back surface serves as a mask in etching the refractory metal layer (22a) over the GaAs back surface. The process of the invention does not require any masks, and results in self-alignment of the refractory metal to the via hole. The process is simple and results in high yield of the MMIC devices on GaAs chips (26).

    摘要翻译： 提供了一种“无掩模”工艺，用于在通过GaAs晶片（12）的通孔（18）中形成诸如钛的难熔金属层（22b），以接触形成在其上的微波单片集成电路（MMIC）器件（10） 其前表面（12a）。 本发明的方法，其防止AuSn焊料（28）在随后的共晶AuSn接合到诸如钼的金属载体（30）的AuSn焊料（28）中填充孔，利用GaAs背面上的抗蚀剂厚度的差异 （12b）并且在通孔中，使得在GaAs背面上除去抗蚀剂（24a）之后残留在通孔中的抗蚀剂（24b）用作在GaAs背面上蚀刻难熔金属层（22a）的掩模 表面。 本发明的方法不需要任何掩模，并且导致耐火金属与通孔的自对准。 该工艺简单，导致GaAs芯片上MMIC器件的产量高（26）。