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    Cyclic redundancy check code generating circuit, semiconductor memory device, and method of driving semiconductor memory device
    2.
    发明授权
    Cyclic redundancy check code generating circuit, semiconductor memory device, and method of driving semiconductor memory device 有权
    循环冗余校验码产生电路，半导体存储器件以及驱动半导体存储器件的方法

    公开(公告)号：US08321777B2

    公开(公告)日：2012-11-27

    申请号：US12002557

    申请日：2007-12-18

    Applicant: Kyung-hyun Kim

    Inventor： Kyung-hyun Kim

    IPC: G06F11/00 ,  H03M13/00

    CPC classification number: H03M13/09 ,  G06F11/1004 ,  H03M13/1102 ,  H03M13/136 ,  H03M13/1515 ,  H03M13/19 ,  H03M13/2957

    Abstract: Disclosed are a semiconductor memory device, and a method of driving the same, and a cyclic redundancy check code generating circuit capable of performing cyclic redundancy check. A semiconductor memory device according to an aspect of the present invention includes a memory cell array, a data processing unit receiving data that is read from the memory cell array and selectively outputting at least some of the data according to ordering information, bit structure information, and burst length information, and a check code generating unit generating a cyclic redundancy check code to detect an error in the data being output, the check code generating unit generating and outputting the cyclic redundancy check code by using the read data, the ordering information, the bit structure information, and the burst length information.

    Abstract translation: 公开了一种半导体存储器件及其驱动方法，以及能够执行循环冗余校验的循环冗余校验码产生电路。 根据本发明的一个方面的半导体存储器件包括存储单元阵列，数据处理单元，接收从存储单元阵列读取的数据，并根据排序信息，比特结构信息选择性地输出数据中的至少一些， 检测码生成部，生成循环冗余校验码，检测出正在输出的数据的错误;校验码生成部，使用读取的数据生成并输出循环冗余校验码，排序信息， 比特结构信息和突发长度信息。

    Method of manufacturing a semiconductor device
    4.
    发明申请
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US20050266647A1

    公开(公告)日：2005-12-01

    申请号：US11082616

    申请日：2005-03-17

    Applicant: Tae-hyun Kim ,  Byoung-moon Yoon ,  Won-jun Lee ,  Yong-sun Ko ,  Kyung-hyun Kim

    Inventor： Tae-hyun Kim ,  Byoung-moon Yoon ,  Won-jun Lee ,  Yong-sun Ko ,  Kyung-hyun Kim

    IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  H01L21/76224 ,  H01L27/115

    Abstract: Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of sidewalls of the trench extends upward beyond a surface of the first field oxide layer. A first liner is formed on the first field oxide layer and on the portion of the sidewalls of the trench that extend upward beyond the first field oxide layer. A second field oxide layer is formed on the first liner and fills the trench. The second field oxide layer and the first liner are each partially removed to expose a top adjacent surface and upper sidewalls of the trench along the active region of the substrate. A dielectric layer is formed on the exposed top adjacent surface and upper sidewalls of the trench. A gate electrode is formed on the dielectric layer.

    Abstract translation: 提供制造半导体器件的方法。 在半导体衬底中形成沟槽。 形成部分填充沟槽的第一场氧化物层。 第一场氧化物层限定与沟槽相邻的衬底的有源区。 沟槽的侧壁的上部向上延伸超过第一场氧化物层的表面。 第一衬垫形成在第一场氧化物层上并且在沟槽的侧壁的部分上方向上延伸超过第一场氧化物层。 在第一衬垫上形成第二场氧化物层并填充沟槽。 每个部分去除第二场氧化物层和第一衬里以沿着衬底的有源区域暴露沟槽的顶部相邻表面和上侧壁。 介电层形成在沟槽的暴露的顶部相邻表面和上侧壁上。 在电介质层上形成栅电极。

    Method for fabricating MOS transistor using selective silicide process
    6.
    发明授权
    Method for fabricating MOS transistor using selective silicide process 有权
    使用选择性硅化物工艺制造MOS晶体管的方法

    公开(公告)号：US06383882B1

    公开(公告)日：2002-05-07

    申请号：US09860591

    申请日：2001-05-21

    Applicant: Sun-wung Lee ,  Jae-phil Boo ,  Kyung-hyun Kim ,  Chang-ki Hong

    Inventor： Sun-wung Lee ,  Jae-phil Boo ,  Kyung-hyun Kim ,  Chang-ki Hong

    IPC: H01L21336

    CPC classification number: H01L21/823468 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823443

    Abstract: A method for fabricating a MOS transistor using a selective silicide process wherein a gate insulating layer and a gate polysilicon layer are sequentially formed on a silicon substrate, and a gate spacer is formed on a side wall of the gate insulating layer and the gate polysilicon layer. Impurity ions are implanted and diffused using the gate spacer and the gate polysilicon layer as a mask layer to form a source/drain region in the substrate. An etching blocking layer is formed to cover the source/drain region, the gate spacer, and the gate polysilicon layer, and then, a dielectric layer to cover the etching blocking layer is formed. The dielectric layer is planarized, and the etching blocking layer on the gate polysilicon layer is exposed. The exposed etching blocking layer and a part of the gate spacer are etched, and a top surface and a top side of the gate polysilicon layer are exposed. A silicide layer is formed over the exposed part of the gate polysilicon layer.

    Abstract translation: 一种使用选择性硅化物工艺制造MOS晶体管的方法，其中在硅衬底上依次形成栅极绝缘层和栅极多晶硅层，并且栅极间隔物形成在栅极绝缘层和栅极多晶硅层的侧壁上 。 使用栅极间隔物和栅极多晶硅层作为掩模层注入和扩散杂质离子，以在衬底中形成源极/漏极区域。 形成蚀刻阻挡层以覆盖源极/漏极区域，栅极间隔物和栅极多晶硅层，然后形成覆盖蚀刻阻挡层的电介质层。 介电层被平坦化，并且露出栅极多晶硅层上的蚀刻阻挡层。 蚀刻暴露的蚀刻阻挡层和栅极间隔物的一部分，并且露出栅极多晶硅层的顶表面和顶侧。 在栅极多晶硅层的暴露部分上形成硅化物层。

    Memory devices and systems including error-correction coding and methods for error-correction coding
    7.
    发明授权
    Memory devices and systems including error-correction coding and methods for error-correction coding 有权
    存储器件和系统包括纠错编码和纠错编码方法

    公开(公告)号：US08627174B2

    公开(公告)日：2014-01-07

    申请号：US12132754

    申请日：2008-06-04

    Applicant: Kyung-hyun Kim ,  Kwang-il Park ,  In-chul Jeong

    Inventor： Kyung-hyun Kim ,  Kwang-il Park ,  In-chul Jeong

    IPC: G11C29/00

    CPC classification number: H04L1/0042

    Abstract: In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer.

    Abstract translation: 一方面，存储器件包括存储单元阵列，将内部数据传送到存储单元阵列和从存储单元阵列发送内部数据的并行内部数据路径，发送和接收外部数据的数据驱动器以及延迟和传送外部数据的数据缓冲器 由数据驱动器接收到内部数据路径，并且延迟并将从存储单元阵列发送的内部数据传送到数据驱动器。 存储装置还包括纠错码发生器，该纠错码产生器基于在内部数据路径上发送的内部数据产生纠错码（EC），延迟由纠错码发生器产生的纠错码的EC缓冲器，EC 发送由EC缓冲器延迟的纠错码的驱动器，以及可变地控制数据缓冲器和EC缓冲器中的至少一个的延迟时间的等待时间控制器。

    NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20120052671A1

    公开(公告)日：2012-03-01

    申请号：US13191571

    申请日：2011-07-27

    Applicant: Choong-kee Seong ,  Kwang-bok Kim ,  Kyung-hyun Kim ,  Jae-jin Shin ,  Hyun-ho Son

    Inventor： Choong-kee Seong ,  Kwang-bok Kim ,  Kyung-hyun Kim ,  Jae-jin Shin ,  Hyun-ho Son

    IPC: H01L21/28 ,  H01L21/302

    CPC classification number: H01L21/32137 ,  H01L21/02068 ,  H01L21/31116 ,  H01L27/11521 ,  H01L29/40114

    Abstract: A method of manufacturing a non-volatile memory device and a non-volatile memory device are provided. The method includes: providing a substrate on which a plurality of charge storage layers that are electrically separated from each other by device isolation layers are formed; recessing the device isolation layers such that an uppermost portion of the device isolation layers is lower than an uppermost portion of the charge storage layers; and dry cleaning first and second sides of each of the charge storage layers that are exposed by the device isolation layers by using a cleaning agent including NF3 gas.

    Abstract translation: 提供一种制造非易失性存储器件和非易失性存储器件的方法。 该方法包括：提供其上形成有通过器件隔离层彼此电分离的多个电荷存储层的衬底; 使器件隔离层凹陷，使得器件隔离层的最上部比电荷存储层的最上部分低; 以及通过使用包括NF 3气体的清洁剂，由装置隔离层暴露的每个电荷存储层的干洗清洁第一和第二侧。

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