公开(公告)号：US20150236726A1

公开(公告)日：2015-08-20

申请号：US14218626

申请日：2014-03-18

Applicant: LSI Corporation

Inventor： Sundararajan Sankaranarayanan ,  AbdelHakim S. Alhussien ,  Erich F. Haratsch ,  Earl Cohen

IPC: H03M13/45 ,  H03M13/37

CPC classification number: H03M13/1111 ,  H03M13/1142 ,  H03M13/3723

Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.

Abstract translation: 数据处理系统包括可操作以接收编码数据的可能性输入，可操作以将解码算法应用于接收的编码数据的似然值并产生解码输出的解码器，以及可操作以产生新的解码器输入值的解码器输入初始化电路 部分地基于在接收的编码数据的似然值未能在解码器中收敛之后接收的编码数据的似然值。

公开(公告)号：US20150199149A1

公开(公告)日：2015-07-16

申请号：US14181893

申请日：2014-02-17

Applicant: LSI Corporation

Inventor： Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/061 ,  G06F3/0617 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688

Abstract: An apparatus includes a plurality of memory devices and a controller. The controller is coupled to the plurality of memory devices and configured to store data in the plurality of memory devices using units of super-blocks. Each super-block comprises a block from each of the plurality of memory devices and the controller balances time efficiency and robustness during collection of statistics from soft reads of each super-block.

Abstract translation: 一种装置包括多个存储装置和控制器。 所述控制器耦合到所述多个存储器设备并且被配置为使用超级块的单元在多个存储器件中存储数据。 每个超块包括来自多个存储器设备中的每一个的块，并且控制器在从每个超块的软读取收集统计信息期间平衡时间效率和鲁棒性。

公开(公告)号：US09036413B2

公开(公告)日：2015-05-19

申请号：US14059229

申请日：2013-10-21

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Abdel-Hakim Alhussien ,  Zhengang Chen ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G11C16/04 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028

Abstract: Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations.

Abstract translation: 通过使用两个或更多个不同的候选参考电压从闪速存储器的一部分读取数据两次或更多次来确定快闪存储器单元电压分布的交点，并确定相应的判定模式。 使用从闪存读取的数据中的判定模式的发生频率来概念地构造直方图。 直方图用于估计交叉点。 采用决策模式可以通过最少的读取操作来确定多个交叉点电压。

公开(公告)号：US20150127883A1

公开(公告)日：2015-05-07

申请号：US14087520

申请日：2013-11-22

Applicant: LSI Corporation

Inventor： Zhengang Chen ,  Erich F. Haratsch ,  Sundararajan Sankaranarayanan

IPC: G06F12/02

CPC classification number: G11C16/28 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1402 ,  G11C7/14 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028

Abstract: Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision. This latter approach is advantageous in that a determination that the precision with which the adjustments can be made is relatively low leads to fewer adjustments having to be made during normal read operations.

Abstract translation: 由离线跟踪过程确定的通道信息和通道条件用于确定是否可以完全避免对读取参考电压的调整，而不会对性能造成不利影响，或者替代地，确定读取参考电压的精度 应作出调整。 如果基于通道条件确定可以完全避免读取参考电压调整，则通过降低在正常读取操作期间需要进行读取参考电压调整的可能性来改善读取性能。 如果基于通道条件确定需要以特定精度进行读取参考电压调整，则以该精度调整读取的参考电压。 后一种方法的优点在于，确定可以进行调整的精度相对较低导致在正常读取操作期间必须进行较少的调整。

公开(公告)号：US20150092489A1

公开(公告)日：2015-04-02

申请号：US14059229

申请日：2013-10-21

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Abdel-Hakim Alhussien ,  Zhengang Chen ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G11C16/10

CPC classification number: G11C16/26 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028

Abstract: Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations.

Abstract translation: 通过使用两个或更多个不同的候选参考电压从闪速存储器的一部分读取数据两次或更多次来确定快闪存储器单元电压分布的交点，并确定相应的判定模式。 使用从闪存读取的数据中的判定模式的发生频率来概念地构造直方图。 直方图用于估计交叉点。 采用决策模式可以通过最少的读取操作来确定多个交叉点电压。

公开(公告)号：US20150162057A1

公开(公告)日：2015-06-11

申请号：US14136283

申请日：2013-12-20

Applicant: LSI Corporation

Inventor： AbdelHakim S. Alhussien ,  Yunxiang Wu ,  Sundararajan Sankaranarayanan ,  Zhengang Chen ,  Erich F. Haratsch

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/14 ,  G11C11/5642 ,  G11C13/004 ,  G11C16/26 ,  G11C16/28

Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.

Abstract translation: 公开了一种具有电路和解码器的装置。 电路被配置为（i）通过将初始参考电压移向窗口中心的量来调整存储器的读通道中的多个参考电压中的初始值，以及（ii）从存储器a读取码字 次数。 窗口限制了参考电压的扫描。 读取的每次重试使用来自参考电压的图案的相应参考电压。 该图案围绕初始参考电压对称地间隔开。 图案适合窗户。 解码器被配置为通过基于读取对码字执行迭代解码过程来生成读取数据。

公开(公告)号：US20150149840A1

公开(公告)日：2015-05-28

申请号：US14135837

申请日：2013-12-20

Applicant: LSI Corporation

Inventor： AbdelHakim S. Alhussien ,  Erich F. Haratsch ,  Sundararajan Sankaranarayanan ,  YingQuan Wu

IPC: H03M13/11 ,  G11C29/12 ,  G11C11/56

CPC classification number: G11C16/28 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/26 ,  G11C29/026 ,  G11C29/028 ,  G11C29/42 ,  G11C2029/4402 ,  H03M13/1117 ,  H03M13/1125

Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.

Abstract translation: 用于读取非易失性存储器的装置包括跟踪模块，其可操作以计算非易失性存储器中的电压电平分布的平均值和方差，并且计算当基于所述非易失性存储器读取非易失性存储器时要使用的至少一个参考电压 平均值和方差，似然发生器可操作以计算在读取非易失性存储器时要使用的至少一个其它参考电压，其中至少一个其它参考电压至少部分地基于预定似然值星座，并且 将从非易失性存储器读取图案映射到似然值，以及读取控制器，其可操作以使用所述至少一个参考电压和所述至少一个其它参考电压来读取所述非易失性存储器以产生所述读取模式。

公开(公告)号：US20150243363A1

公开(公告)日：2015-08-27

申请号：US14195058

申请日：2014-03-03

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Zhengang Chen ,  AbdelHakim S. Alhussien ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G11C16/26

CPC classification number: G11C11/5642 ,  G06F11/1048 ,  G06F11/1072 ,  G11C29/52

Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values.

Abstract translation: 公开了一种具有电路和与非易失性存储器的接口的装置。 电路被配置为（i）执行对存储在非易失性存储器中的数据的软判决解码的一个或多个尝试，其中软判决解码使用存储在表中的多个对数似然比值，（ii）生成一个 或更多调整的对数似然比值，通过将响应于使用对数似然比值对数据进行解码的一个或多个对数似然比值来增加常数值，以及（iii）使用调整后的记录重新解码数据 似然比值。