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公开(公告)号：US06661097B1
公开(公告)日：2003-12-09
申请号：US10287155
申请日：2002-11-01
申请人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
发明人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.
摘要翻译： 在铜后端集成电路技术中，使用低k有机基层间电介质的先进技术具有碳污染的问题，在使用氧化物作为电介质的电路中不会发生这种问题。 用于铜线的复合衬里层使用Ti作为底层，其具有吸除碳和其它污染物的性质。 通过添加一层分离Ti和铜的TiN层，避免了与铜反应形成高电阻率化合物的Ti的已知问题。
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2.发明授权Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer 失效在具有覆盖层的半导体互连结构上沉积金属层的方法公开(公告)号：US07241696B2
公开(公告)日：2007-07-10
申请号：US10318606
申请日：2002-12-11
申请人： Larry Clevenger , Timothy Joseph Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik Kumar , Douglas C. La Tulipe, Jr. , Soon-Cheon Seo , Andrew Herbert Simon , Yun-Yu Wang , Chih-Chao Yang , Haining Yang
发明人： Larry Clevenger , Timothy Joseph Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik Kumar , Douglas C. La Tulipe, Jr. , Soon-Cheon Seo , Andrew Herbert Simon , Yun-Yu Wang , Chih-Chao Yang , Haining Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76847 , H01L21/76865
摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
摘要翻译： 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体被覆盖层和电介质层覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体。 在溅射蚀刻的过程中，覆盖层被再沉积到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。
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公开(公告)号：US07504337B2
公开(公告)日：2009-03-17
申请号：US11690432
申请日：2007-03-23
IPC分类号： H01L21/461 , H01L21/302
摘要： Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 μm polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 μm diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 μm diamond polishing particles.
摘要翻译： 公开了均匀地延迟IC芯片的方法。 一个实施例包括：在包括其Al层的晶片上执行灰分并蚀刻Al层; 使用包含约30μm的抛光颗粒的浆料抛光晶片的边缘; 通过使用包含大约9μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来去除铝层和至少一个金属层; 通过使用包含大约3μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光，将任何剩余的金属层除去到第一金属层; 通过使用包括大约1毫米金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来除去任何划痕; 并且通过使用包含大约0.25μm金刚石抛光颗粒的胶体浆料进行抛光将第一金属层去除到多导体层。
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公开(公告)号：US20080233751A1
公开(公告)日：2008-09-25
申请号：US11690432
申请日：2007-03-23
IPC分类号： H01L21/461
摘要： Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 μm polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 μm diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 μm diamond polishing particles.
摘要翻译： 公开了均匀地延迟IC芯片的方法。 一个实施例包括：在包括其Al层的晶片上执行灰分并蚀刻Al层; 使用包含约30μm的抛光颗粒的浆料抛光晶片的边缘; 通过使用包含大约9μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来去除铝层和至少一个金属层; 通过使用包含大约3μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光，将任何剩余的金属层除去到第一金属层; 通过使用包括大约1毫米金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来除去任何划痕; 并且通过使用包含大约0.25μm金刚石抛光颗粒的胶体浆料进行抛光将第一金属层去除到多导体层。
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公开(公告)号：US08368069B2
公开(公告)日：2013-02-05
申请号：US13360270
申请日：2012-01-27
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L23/5252 , H01L21/76823 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.
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公开(公告)号：US07498256B2
公开(公告)日：2009-03-03
申请号：US11465865
申请日：2006-08-21
申请人： Randolph F. Knarr , Christopher D. Sheraw , Andrew H. Simon , Anna Topol , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Randolph F. Knarr , Christopher D. Sheraw , Andrew H. Simon , Anna Topol , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L21/00
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Contact via structures using a hybrid barrier layer, are disclosed. One contact via structure includes: an opening through a dielectric to a silicide region; a first layer in the opening in direct contact with the silicide region, wherein the first layer is selected from the group consisting of: titanium (Ti) and tungsten nitride (WN); at least one second layer over the first layer, the at least one second layer selected from the group consisting of: tantalum nitride (TaN), titanium nitride (TiN), tantalum (Ta), ruthenium (Ru), rhodium (Rh), platinum (Pt) and cobalt (Co); a seed layer for copper (Cu); and copper (Cu) filling a remaining portion of the opening.
摘要翻译： 公开了通过使用混合阻挡层的结构的接触。 一个接触通孔结构包括：通过电介质到硅化物区的开口; 与所述硅化物区直接接触的所述开口中的第一层，其中所述第一层选自：钛（Ti）和氮化钨（WN）; 在第一层上的至少一个第二层，选自氮化钽（TaN），氮化钛（TiN），钽（Ta），钌（Ru），铑（Rh），铑 铂（Pt）和钴（Co）; 铜（Cu）种子层; 和填充开口的剩余部分的铜（Cu）。
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公开(公告)号：US06180521B2
公开(公告)日：2001-01-30
申请号：US09225598
申请日：1999-01-06
申请人： Patrick W. DeHaven , Anthony G. Domenicucci , Lynne M. Gignac , Glen L. Miles , Prabhat Tiwari , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
发明人： Patrick W. DeHaven , Anthony G. Domenicucci , Lynne M. Gignac , Glen L. Miles , Prabhat Tiwari , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
IPC分类号： H01L2128
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/76855 , H01L21/76856 , H01L21/76864
摘要： A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500° C. to about 700° C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.
摘要翻译： 一种用于形成具有平坦界面的导电触头的工艺。 将含有铌和钛的层沉积在硅衬底上，所得结构在约500℃至约700℃的含氮气氛中退火。通过该过程，硅化物和硅之间的平坦界面是 在退火时形成不太可能导致结漏电。 退火步骤还产生更均匀的双层，这是在随后的钨沉积期间防止钨侵蚀的更好的屏障。 还形成更大的硅化物晶粒，使得产生更少的晶界，减少晶界中的金属扩散。 该过程可用于形成非常小的器件和浅结的接触，例如当前和未来的半导体器件所需要的。
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公开(公告)号：US08466443B2
公开(公告)日：2013-06-18
申请号：US12827197
申请日：2010-06-30
IPC分类号： H01L29/02
CPC分类号： H01L45/1616 , G11C17/14 , H01C7/1013 , H01C7/105 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected to the semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 102, more preferably 103 and most preferably 104 when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.
摘要翻译： 公开了一种包括半导体器件和连接到半导体器件的VSR的一次（WO）只读存储器（ROM）器件的电压敏感电阻器（VSR）。 VSR WO ROM设备是一次写入只读设备。 VSR包括具有残留钛 - 碳键合的CVD氮化钛层，使得VSR是形成的电阻的，并且当预定的电压和电流被施加到电阻时，可以变得更小的电阻性为102，更优选为103，最优选为104。 VSR。 多个VSR WO ROM器件可以被布置成在3-D堆栈中形成高密度可编程逻辑电路。 还公开了形成VSR WO ROM器件的方法。
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公开(公告)号：US20120129340A1
公开(公告)日：2012-05-24
申请号：US13360248
申请日：2012-01-27
IPC分类号： H01L21/283
CPC分类号： H01L23/5252 , H01L21/76823 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.
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公开(公告)号：US20120126367A1
公开(公告)日：2012-05-24
申请号：US13360277
申请日：2012-01-27
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , H01L21/76823 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.
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