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公开(公告)号：US09477244B2
公开(公告)日：2016-10-25
申请号：US14381186
申请日：2014-01-10
Applicant: Lattice Semiconductor Corporation
Inventor： Kexin Luo , Fangqing Chu , Yu Shen , Zhi Wu , Inyeol Lee
Abstract: Embodiments of the invention are generally directed to a linear regulator with improved power supply ripple rejection. An embodiment of an apparatus includes an linear regulator to receive a system power supply and to generate a regulated power supply; a first voltage reference generator to generate a first voltage reference for the linear regulator; a second voltage reference generator to generate a second voltage reference for the linear regulator; and a voltage reference and power switcher. In some embodiments, the voltage reference and power switcher is to switch a voltage reference for the linear regulator from the first voltage reference to the second voltage reference and is to switch a part of a power supply for the linear regulator from the system power supply to the regulated power supply.
Abstract translation: 本发明的实施例通常涉及具有改进的电源纹波抑制的线性调节器。 装置的实施例包括线性调节器，用于接收系统电源并产生稳压电源; 第一参考电压发生器，用于产生线性调节器的第一电压基准; 第二参考发生器，用于为所述线性调节器产生第二参考电压; 以及电压基准和电源切换器。 在一些实施例中，电压参考和功率切换器将线性调节器的电压参考值从第一参考电压切换到第二参考电压，并将用于线性稳压器的电源的一部分从系统电源切换到 稳压电源。
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公开(公告)号：US09948234B2
公开(公告)日：2018-04-17
申请号：US14440186
申请日：2014-07-24
Applicant: LATTICE SEMICONDUCTOR CORPORATION
IPC: H03L7/00 , H03B5/04 , H03L7/099 , H03K3/0231 , H03L7/093
CPC classification number: H03B5/04 , H03B2200/0038 , H03K3/0231 , H03L7/00 , H03L7/093 , H03L7/099
Abstract: A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.
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公开(公告)号：US20180198409A1
公开(公告)日：2018-07-12
申请号：US15917550
申请日：2018-03-09
Applicant: Lattice Semiconductor Corporation
IPC: H03B5/04 , H03L7/099 , H03L7/093 , H03L7/00 , H03K3/0231
CPC classification number: H03B5/04 , H03B2200/0038 , H03K3/0231 , H03L7/00 , H03L7/093 , H03L7/099
Abstract: A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.
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Patent Agency Ranking
公开(公告)号：US09484939B2
公开(公告)日：2016-11-01
申请号：US14383865
申请日：2014-05-16
Applicant: LATTICE SEMICONDUCTOR CORPORATION
Inventor： Kexin Luo , Kai Zhou , Shengguo Cao , Lingfen Yue , Fangquing Chu , Yu Shen , Zhi Wu
CPC classification number: H03L7/1976 , G06F1/04 , H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/193 , H03M3/30
Abstract: Embodiments describe techniques for utilizing fractional-N phase locked loops (PLL). Some embodiments describe a fractional-divider based fractional-N PLL for a spread spectrum clock (SSC) generator that utilizes phase average techniques to suppress phase interpolator nonlinearity. Some embodiments describe a fractional-N PLL based on fractional dividers with hybrid finite impulse response (FIR) filtering. Some embodiments describe a small size and low power divider for a hybrid FIR fractional-N PLL.
Abstract translation: 实施例描述了利用分数N锁相环（PLL）的技术。 一些实施例描述了利用相位平均技术来抑制相位内插器非线性的扩展频谱时钟（SSC）发生器的基于分数分频器的分数N PLL。 一些实施例描述了基于具有混合有限脉冲响应（FIR）滤波的分数分频器的分数N PLL。 一些实施例描述了用于混合FIR分数N PLL的小尺寸和低功率分配器。
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公开(公告)号：US20160248376A1
公开(公告)日：2016-08-25
申请号：US14440186
申请日：2014-07-24
Applicant: LATTICE SEMICONDUCTOR CORPORATION
CPC classification number: H03B5/04 , H03B2200/0038 , H03K3/0231 , H03L7/00 , H03L7/093 , H03L7/099
Abstract: A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.
Abstract translation: 公开了压控振荡器（VCO）。 VCO包括放大器，其接收控制信号和反馈信号，并且基于控制信号和反馈信号之间的差产生放大的输出信号。 VCO还包括基于放大器输出信号产生振荡输出信号的电路。 此外，VCO包括基于放大器的输出产生反馈信号的反馈放大器。 反馈放大器包括与第二电阻并联连接的第一电阻器，第二电阻器具有可调电阻。
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公开(公告)号：US10523153B2
公开(公告)日：2019-12-31
申请号：US15917550
申请日：2018-03-09
Applicant: Lattice Semiconductor Corporation
IPC: H03B5/04 , H03L7/00 , H03L7/099 , H03K3/0231 , H03L7/093
Abstract: A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.
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公开(公告)号：US10116428B2
公开(公告)日：2018-10-30
申请号：US15312149
申请日：2014-05-20
Applicant: Lattice Semiconductor Corporation
Inventor： Qiming Wu , Kai Lei , Fei Song , Kai Zhou , Gijung Ahn , Zhi Wu , Min-Kyu Kim
Abstract: Systems, devices and methods for analog echo cancellation for high speed full duplex data transmissions, which include a first set of differential nodes to receive reception data and transmission data, a second set of differential nodes to receive the transmission data, and a subtraction circuit to receive data from the first set of differential nodes and data from the second set of differential nodes. The subtraction circuit includes a plurality of capacitors to receive data from each of the first and second sets differential nodes, and a termination circuit for providing DC termination voltage to subtract the data of the second set of differential nodes from the data of the first set of differential nodes to eliminate echo from the reception data received at the first set differential nodes.
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公开(公告)号：US20170085359A1
公开(公告)日：2017-03-23
申请号：US15312149
申请日：2014-05-20
Applicant: LATTICE SEMICONDUCTOR CORPORATION
Inventor： Qiming Wu , Kai Lei , Fei Song , Kai Zhou , Gijung Ahn , Zhi Wu , Min-Kyu Kim
IPC: H04L5/14
CPC classification number: H04L5/1461 , H04B3/23 , H04B3/30
Abstract: Systems, devices and methods for analog echo cancellation for high speed full duplex data transmissions, which include a first set of differential nodes to receive reception data and transmission data, a second set of differential nodes to receive the transmission data, and a subtraction circuit to receive data from the first set of differential nodes and data from the second set of differential nodes. The subtraction circuit includes a plurality of capacitors to receive data from each of the first and second sets differential nodes, and a termination circuit for providing DC termination voltage to subtract the data of the second set of differential nodes from the data of the first set of differential nodes to eliminate echo from the reception data received at the first set differential nodes.
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