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    Method for reducing resist height erosion in a gate etch process
    2.
    发明授权
    Method for reducing resist height erosion in a gate etch process 有权
    在栅极蚀刻工艺中降低抗蚀剂高度腐蚀的方法

    公开(公告)号：US07005386B1

    公开(公告)日：2006-02-28

    申请号：US10656467

    申请日：2003-09-05

    申请人： Scott Bell ,  Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Ashok M. Khathuria

    发明人： Scott Bell ,  Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Ashok M. Khathuria

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0274 ,  H01L21/31058

    摘要： According to one exemplary embodiment, a method for reducing resist height erosion in a gate etch process comprises a step of forming a first resist mask on an anti-reflective coating layer situated over a substrate, where the first resist mask has a first width. The anti-reflective coating layer may be, for example, an organic material. The method further comprises a step of trimming the first resist mask to form a second resist mask, where the second resist mask has a second width, and where the second width is less than the first width. The step of trimming the first resist mask may further comprise, for example, etching the anti-reflective coating layer. According to this exemplary embodiment, the method further comprises a step of performing an HBr plasma treatment on the second resist mask, wherein the HBr plasma treatment causes a vertical etch rate of the second resist mask to decrease.

    摘要翻译： 根据一个示例性实施例，用于降低栅极蚀刻工艺中的抗蚀剂高度腐蚀的方法包括在位于衬底上的抗反射涂层上形成第一抗蚀剂掩模的步骤，其中第一抗蚀剂掩模具有第一宽度。 抗反射涂层可以是例如有机材料。 该方法还包括修整第一抗蚀剂掩模以形成第二抗蚀剂掩模的步骤，其中第二抗蚀剂掩模具有第二宽度，并且其中第二宽度小于第一宽度。 修整第一抗蚀剂掩模的步骤还可以包括例如蚀刻抗反射涂层。 根据该示例性实施例，该方法还包括在第二抗蚀剂掩模上执行HBr等离子体处理的步骤，其中HBr等离子体处理导致第二抗蚀剂掩模的垂直蚀刻速率降低。

    Hard mask spacer for sublithographic bitline
    4.
    发明授权
    Hard mask spacer for sublithographic bitline 有权
    用于亚光刻位线的硬掩模垫片

    公开(公告)号：US06962849B1

    公开(公告)日：2005-11-08

    申请号：US10729732

    申请日：2003-12-05

    申请人： Tazrien Kamal ,  Weidong Qian ,  Kouros Ghandehari ,  Taraneh Jamali-Beh ,  Mark T. Ramsbey ,  Ashok M. Khathuria

    发明人： Tazrien Kamal ,  Weidong Qian ,  Kouros Ghandehari ,  Taraneh Jamali-Beh ,  Mark T. Ramsbey ,  Ashok M. Khathuria

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.

    摘要翻译： 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 在形成过程中使用间隔物来减小存储器中的掩埋位线的尺寸，这适用于存储用于计算机等的数据。 较小（例如较窄）的位线有助于增加打包密度，同时保持位线之间的有效通道长度。 位线之间的间隔允许存储在电荷俘获层内的通道上方的双位保持充分分离，以便彼此不干扰。 以这种方式，一个位可以被操作（例如，用于读取，写入或擦除操作）而基本上或不利地影响另一个位。 此外，保留位分离，并且减轻了可能由窄通道产生的漏电流，串扰以及其他不利影响，并且允许存储器件根据需要进行操作。

    Self aligned memory element and wordline
    6.
    发明授权
    Self aligned memory element and wordline 有权
    自对准存储元件和字线

    公开(公告)号：US07220985B2

    公开(公告)日：2007-05-22

    申请号：US10314591

    申请日：2002-12-09

    申请人： Patrick K. Cheung ,  Ashok M. Khathuria

    发明人： Patrick K. Cheung ,  Ashok M. Khathuria

    IPC分类号： H01L21/00 ,  H01L29/08 ,  H01L35/24 ,  H01L51/00

    CPC分类号： H01L27/28

    摘要： An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e.g., copper) layer (e.g., bitline). The memory cells are connected to a second conductive layer (e.g., forming a wordline), and more particularly the top of the electrode layer of the memory cells to the second conductive layer. Optionally, a conductivity facilitating layer is formed over the conductive layer. Dielectric material separates the memory cells. The memory cells are self-aligned with the bitlines formed in the first conductive layer and the wordlines formed in the second conductive layer.

    摘要翻译： 提供了一种有机聚合物记忆单元，其具有形成在第一导电（例如铜）层（例如位线）上的有机聚合物层和电极层。 存储单元连接到第二导电层（例如，形成字线），更具体地，将存储器单元的电极层的顶部连接到第二导电层。 可选地，导电促进层形成在导电层上。 电介质材料分离存储单元。 存储单元与形成在第一导电层中的位线和形成在第二导电层中的字线自对准。

    Method of achieving stable deep ultraviolet (DUV) resist etch rate for gate critical dimension (CD)
    7.
    发明授权
    Method of achieving stable deep ultraviolet (DUV) resist etch rate for gate critical dimension (CD) 失效
    实现稳定的深紫外（DUV）栅极临界尺寸（CD）的抗蚀刻蚀刻速率的方法

    公开(公告)号：US06455333B1

    公开(公告)日：2002-09-24

    申请号：US09796382

    申请日：2001-02-28

    申请人： Ashok M. Khathuria

    发明人： Ashok M. Khathuria

    IPC分类号： H01L2100

    CPC分类号： H01L21/32139 ,  H01L21/28123

    摘要： A method of stabilizing the DUV resist etch rate for a gate critical dimension, especially for a CD≦75 &mgr;m. More specifically, the present invention provides a method for stabilizing a deep ultraviolet (DUV) resist etch rate by utilizing the directly proportionate relationship between the lateral erosion and a vertical etch rate. The present invention method provides control of lateral erosion of the DUV resist by measuring the vertical etch rate component. The present invention method involves conditioning (seasoning) an etch chamber with a conditioning wafer having a unique stack which results in consistent and stable DUV resist etch rates. The present invention seasoning is applied before processing of a product wafer lot for providing better control of the gate CD targeting, and thereby eliminating a “first wafer” effect.

    摘要翻译： 稳定栅极临界尺寸的DUV抗蚀剂蚀刻速率的方法，特别是对于CD <=75μm的稳定剂。 更具体地，本发明提供了一种通过利用横向侵蚀和垂直蚀刻速率之间的直接成比例的关系来稳定深紫外（DUV）抗蚀剂蚀刻速率的方法。 本发明方法通过测量垂直蚀刻速率分量来提供对DUV抗蚀剂横向侵蚀的控制。 本发明的方法包括用具有独特叠层的调节晶片调节（调味）蚀刻室，这导致一致且稳定的DUV抗蚀剂蚀刻速率。 在处理产品晶片批次之前应用本发明的调味料，以便更好地控制栅极CD靶向，从而消除“第一晶片”效应。

    Self aligned memory element and wordline
    8.
    发明授权
    Self aligned memory element and wordline 有权
    自对准存储元件和字线

    公开(公告)号：US07645632B2

    公开(公告)日：2010-01-12

    申请号：US11750724

    申请日：2007-05-18

    申请人： Patrick K. Cheung ,  Ashok M. Khathuria

    发明人： Patrick K. Cheung ,  Ashok M. Khathuria

    IPC分类号： H01L51/40

    CPC分类号： H01L27/28

    摘要： An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e.g., copper) layer (e.g., bitline). The memory cells are connected to a second conductive layer (e.g., forming a wordline), and more particularly the top of the electrode layer of the memory cells to the second conductive layer. Optionally, a conductivity facilitating layer is formed over the conductive layer. Dielectric material separates the memory cells. The memory cells are self-aligned with the bitlines formed in the first conductive layer and the wordlines formed in the second conductive layer.

    摘要翻译： 提供了一种有机聚合物记忆单元，其具有形成在第一导电（例如铜）层（例如位线）上的有机聚合物层和电极层。 存储单元连接到第二导电层（例如，形成字线），更具体地，将存储器单元的电极层的顶部连接到第二导电层。 可选地，导电促进层形成在导电层上。 电介质材料分离存储单元。 存储单元与形成在第一导电层中的位线和形成在第二导电层中的字线自对准。

    Silicon containing material for patterning polymeric memory element
    9.
    发明授权
    Silicon containing material for patterning polymeric memory element 有权
    含硅材料用于图案化聚合物记忆元件

    公开(公告)号：US06803267B1

    公开(公告)日：2004-10-12

    申请号：US10614484

    申请日：2003-07-07

    申请人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

    发明人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

    IPC分类号： H01L21336

    CPC分类号： H01L27/28 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0018

    摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.

    摘要翻译： 本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料 上电极通过有机半导体材料和被动材料到下电极。 有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。 此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。 分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。