公开(公告)号：US08512849B2

公开(公告)日：2013-08-20

申请号：US11836253

申请日：2007-08-09

申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

IPC分类号： B32B3/30

CPC分类号： H05K3/40 ,  H01B17/66 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76822 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T156/1039 ,  Y10T156/1082 ,  Y10T428/24521 ,  Y10T428/24529 ,  Y10T428/24537 ,  Y10T428/24612 ,  Y10T428/24711 ,  H01L2924/00

摘要： Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.

公开(公告)号：US20090041989A1

公开(公告)日：2009-02-12

申请号：US11836253

申请日：2007-08-09

申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

IPC分类号： B32B3/28 ,  B05D3/04 ,  B05D3/06

CPC分类号： H05K3/40 ,  H01B17/66 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76822 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T156/1039 ,  Y10T156/1082 ,  Y10T428/24521 ,  Y10T428/24529 ,  Y10T428/24537 ,  Y10T428/24612 ,  Y10T428/24711 ,  H01L2924/00

摘要： Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.

摘要翻译： 包含在互连叠层中具有纳米级波纹界面的界面的介电复合结构提供了增强的粘合强度和界面断裂韧性。 还描述了进一步包含波纹粘合促进剂层以进一步增加本征界面粘合性的复合结构。 还描述了使用自组装聚合物体系和图案转移方法形成纳米级波纹界面以实现这些结构的方法。

公开(公告)号：US07989291B2

公开(公告)日：2011-08-02

申请号：US12712369

申请日：2010-02-25

申请人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

发明人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

IPC分类号： H01L29/72

CPC分类号： H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.

摘要翻译： 在基板上形成具有线性边缘的突出结构。 突出结构可以是场效应晶体管的栅极线。 应力产生衬垫沉积在衬底上。 含有至少两种不混溶的聚合物嵌段组分的非感光性自组装嵌段共聚物层沉积在应力产生衬里上，并进行退火以允许不相容的组分相分离。 聚合物抗蚀剂被显影以除去至少两个聚合物嵌段组分中的至少一个，其由于突出结构的线性边缘而形成嵌套线的图案。 在自对准和自组装的聚合物抗蚀剂中形成线性纳米级条纹。 将应力产生层图案化成具有亚光刻宽度的线性应力产生条纹。 线性应力产生条纹沿其长度方向提供主要的单轴应力，向下面的半导体器件提供各向异性的应力。

公开(公告)号：US20100151638A1

公开(公告)日：2010-06-17

申请号：US12712369

申请日：2010-02-25

申请人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

发明人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

IPC分类号： H01L21/336 ,  H01L21/30

CPC分类号： H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.

摘要翻译： 在基板上形成具有线性边缘的突出结构。 突出结构可以是场效应晶体管的栅极线。 应力产生衬垫沉积在衬底上。 含有至少两种不混溶的聚合物嵌段组分的非感光性自组装嵌段共聚物层沉积在应力产生衬里上，并进行退火以允许不相容的组分相分离。 聚合物抗蚀剂被显影以除去至少两个聚合物嵌段组分中的至少一个，其由于突出结构的线性边缘而形成嵌套线的图案。 在自对准和自组装的聚合物抗蚀剂中形成线性纳米级条纹。 将应力产生层图案化成具有亚光刻宽度的线性应力产生条纹。 线性应力产生条纹沿其长度方向提供主要的单轴应力，向下面的半导体器件提供各向异性的应力。

公开(公告)号：US07696542B2

公开(公告)日：2010-04-13

申请号：US12017557

申请日：2008-01-22

申请人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

发明人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

IPC分类号： H01L29/72

CPC分类号： H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.

摘要翻译： 在基板上形成具有线性边缘的突出结构。 突出结构可以是场效应晶体管的栅极线。 应力产生衬垫沉积在衬底上。 含有至少两种不混溶的聚合物嵌段组分的非感光性自组装嵌段共聚物层沉积在应力产生衬里上，并进行退火以允许不相容的组分相分离。 聚合物抗蚀剂被显影以除去至少两个聚合物嵌段组分中的至少一个，其由于突出结构的线性边缘而形成嵌套线的图案。 在自对准和自组装的聚合物抗蚀剂中形成线性纳米级条纹。 将应力产生层图案化成具有亚光刻宽度的线性应力产生条纹。 线性应力产生条纹沿其长度方向提供主要的单轴应力，向下面的半导体器件提供各向异性的应力。

公开(公告)号：US20090184374A1

公开(公告)日：2009-07-23

申请号：US12017557

申请日：2008-01-22

申请人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

发明人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.

摘要翻译： 在基板上形成具有线性边缘的突出结构。 突出结构可以是场效应晶体管的栅极线。 应力产生衬垫沉积在衬底上。 含有至少两种不混溶的聚合物嵌段组分的非感光性自组装嵌段共聚物层沉积在应力产生衬里上，并进行退火以允许不相容的组分相分离。 聚合物抗蚀剂被显影以除去至少两个聚合物嵌段组分中的至少一个，其由于突出结构的线性边缘而形成嵌套线的图案。 在自对准和自组装的聚合物抗蚀剂中形成线性纳米级条纹。 将应力产生层图案化成具有亚光刻宽度的线性应力产生条纹。 线性应力产生条纹沿其长度方向提供主要的单轴应力，向下面的半导体器件提供各向异性的应力。

公开(公告)号：US08343868B2

公开(公告)日：2013-01-01

申请号：US13005201

申请日：2011-01-12

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越到多个互连的侧壁。

公开(公告)号：US07892940B2

公开(公告)日：2011-02-22

申请号：US11851123

申请日：2007-09-06

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越至少一个互连的侧壁。

公开(公告)号：US08129286B2

公开(公告)日：2012-03-06

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。

公开(公告)号：US20080254630A1

公开(公告)日：2008-10-16

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. EDELSTEIN ,  Matthew E. Colburn ,  Edward C. Cooney ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. EDELSTEIN ,  Matthew E. Colburn ,  Edward C. Cooney ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/311

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。