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    Operating vehicular processor-based systems
    1.
    发明授权
    Operating vehicular processor-based systems 有权
    基于车载处理器的系统

    公开(公告)号：US06249739B1

    公开(公告)日：2001-06-19

    申请号：US09387349

    申请日：1999-08-31

    申请人： Lee P. Noehring ,  Bruce L. Fleming

    发明人： Lee P. Noehring ,  Bruce L. Fleming

    IPC分类号： G06F130

    CPC分类号： G06F11/1441 ,  G06F1/305

    摘要： A processor-based system in a vehicle may be quickly suspended to a lower power consumption state after detecting a signal indicative of engine cranking. Advantageously, the system may be caused to enter the lower power consumption state prior to the time that power is reduced as a result of engine cranking. If the operating system is active when the signal is detected, a routine may be called which causes device contexts to be saved before returning the system to a reduced power consumption state. Otherwise, if the operating system is inactive, an interrupt handler may be called which immediately returns the system to a reduced power consumption state. In this way, the system may be reliably restored to a lower power consumption state before being exposed to the power reduction inherent in engine cranking.

    摘要翻译： 在检测到指示发动机起动的信号之后，车辆中的基于处理器的系统可以被快速地暂停到较低的功率消耗状态。 有利地，可以在由于发动机起动而减少功率的时间之前使系统进入较低的功率消耗状态。 如果在检测到信号时操作系统处于活动状态，则可能会调用一个程序，这样可以在将系统恢复到降低功耗状态之前保存设备上下文。 否则，如果操作系统不活动，则可以调用中断处理程序，该中断处理程序立即将系统返回到降低的功耗状态。 以这种方式，在暴露于发动机起动中固有的功率降低之前，系统可以可靠地恢复到较低的功率消耗状态。

    Method to control core duty cycles using low power modes
    4.
    发明授权
    Method to control core duty cycles using low power modes 有权
    使用低功耗模式控制核心占空比的方法

    公开(公告)号：US07774626B2

    公开(公告)日：2010-08-10

    申请号：US11729792

    申请日：2007-03-29

    申请人： Bruce L. Fleming

    发明人： Bruce L. Fleming

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3228

    摘要： A processor starting a duty cycle timer with a specified duty cycle period and a specified power state, and if the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer, if the timer has not expired and if an interrupt other than a timer tick interrupt is received, canceling the duty cycle timer in response to the interrupt other than a timer tick interrupt.

    摘要翻译： 处理器以指定的占空比周期和指定的功率状态启动占空比定时器，并且如果占空比定时器期满，则响应于定时器的到期将处理器置于指定的电源状态，如果定时器尚未到期 并且如果接收到定时器中断以外的中断，则响应于定时器复选中断以外的中断，取消占空比定时器。

    METHOD, SYSTEM AND APPARATUS FOR LOW-POWER STORAGE OF PROCESSOR CONTEXT INFORMATION
    5.
    发明申请
    METHOD, SYSTEM AND APPARATUS FOR LOW-POWER STORAGE OF PROCESSOR CONTEXT INFORMATION 有权
    用于处理器上下文信息的低功率存储的方法，系统和装置

    公开(公告)号：US20130124898A1

    公开(公告)日：2013-05-16

    申请号：US13736829

    申请日：2013-01-08

    申请人： Bruce L. Fleming ,  Ashish V. Choubal ,  Sanjoy K. Mondal ,  Belliappa M. Kuttanna

    发明人： Bruce L. Fleming ,  Ashish V. Choubal ,  Sanjoy K. Mondal ,  Belliappa M. Kuttanna

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3287 ,  G06F1/3203

    摘要： A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core.

    摘要翻译： 一种用于保存和/或检索用于电力状态转换的处理器核心的上下文信息的方法和系统。 处理器核心驻留在多个功率状态之间不同地转换的复杂功率域。 处理器核心包括用于存储和检索处理器核心上下文信息的本地上下文存储区域。 低功耗上下文存储位于复合功率域外的标称功率域。 基于复电力域的功率状态转换是否包括向处理器核心断电的过渡，将处理器核心的上下文信息存储到低功率上下文存储器。

    Method to control core duty cycles using low power modes
    9.
    发明申请
    Method to control core duty cycles using low power modes 有权
    使用低功耗模式控制核心占空比的方法

    公开(公告)号：US20080244285A1

    公开(公告)日：2008-10-02

    申请号：US11729792

    申请日：2007-03-29

    申请人： Bruce L. Fleming

    发明人： Bruce L. Fleming

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3228

    摘要： A processor starting a duty cycle timer with a specified duty cycle period and a specified power state, and if the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer, if the timer has not expired and if an interrupt other than a timer tick interrupt is received, canceling the duty cycle timer in response to the interrupt other than a timer tick interrupt.

    摘要翻译： 处理器以指定的占空比周期和指定的功率状态启动占空比定时器，并且如果占空比定时器期满，则响应于定时器的到期将处理器置于指定的电源状态，如果定时器尚未到期 并且如果接收到定时器中断以外的中断，则响应于定时器复选中断以外的中断，取消占空比定时器。

    Booting from a reprogrammable memory on an unconfigured bus by modifying boot device address
    10.
    发明授权
    Booting from a reprogrammable memory on an unconfigured bus by modifying boot device address 失效
    通过修改引导设备地址，在未配置的总线上从可重新编程的内存引导

    公开(公告)号：US06622244B1

    公开(公告)日：2003-09-16

    申请号：US09372004

    申请日：1999-08-11

    申请人： Mark E. Eidson ,  Bruce L. Fleming

    发明人： Mark E. Eidson ,  Bruce L. Fleming

    IPC分类号： G06F924

    CPC分类号： G06F9/4403

    摘要： Boot up instructions may be stored on a memory coupled to the peripheral component interconnect (PCI) bus. These instructions may be accessed, despite the fact that peripheral component interconnect devices are normally not active during the boot up sequence. As a result, both the basic input/output system and other information may be stored on a reprogrammable memory coupled to the PCI bus. In some embodiments, this may reduce costs by avoiding the need for two semiconductor memories, one on the PCI bus and the other on a legacy bus.

    摘要翻译： 引导指令可以存储在耦合到外围组件互连（PCI）总线的存储器上。 尽管外部组件互连设备在启动顺序期间通常不是活动的，但是可以访问这些指令。 因此，基本输入/输出系统和其他信息都可以存储在与PCI总线耦合的可再编程存储器上。 在一些实施例中，这可以通过避免需要两个半导体存储器来降低成本，一个在PCI总线上，另一个在传统总线上。