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    INDUCED THERMAL GRADIENTS
    5.
    发明申请
    INDUCED THERMAL GRADIENTS 有权
    诱导热梯度

    公开(公告)号：US20120249219A1

    公开(公告)日：2012-10-04

    申请号：US13336806

    申请日：2011-12-23

    申请人： Kenneth D. Shoemaker

    发明人： Kenneth D. Shoemaker

    IPC分类号： H03K5/00

    CPC分类号： G06F1/3275 ,  G01K3/08 ,  G06F1/206 ,  G06F1/3225 ,  Y02D10/14 ,  Y02D10/16

    摘要： A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

    摘要翻译： 确定第一模具上的第一热传感器和第二热传感器之间的温度差。 温度差从第一管芯传送到第二管芯上的电路。 确定来自第二管芯上的热传感器的温度。 在第二管芯上利用来自热传感器的温度差和温度来修改第二管芯上的一个或多个电路的操作特性。

    Physical address size selection and page size selection in an address translator
    6.
    发明授权
    Physical address size selection and page size selection in an address translator 失效
    地址翻译器中的物理地址大小选择和页面大小选择

    公开(公告)号：US5802605A

    公开(公告)日：1998-09-01

    申请号：US756184

    申请日：1996-11-25

    申请人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

    发明人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1009 ,  G06F2212/652

    摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.

    摘要翻译： 这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。 可以选择不同的内存大小和不同的页面大小。 地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。 地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。 线性地址到字段的格式取决于所选的内存大小和所选的页面大小。 对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组 的页表条目。 表中条目的大小取决于所选的内存大小。 表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。

    INDICATING CRITICAL BATTERY STATUS IN MOBILE DEVICES
    7.
    发明申请
    INDICATING CRITICAL BATTERY STATUS IN MOBILE DEVICES 有权
    指出移动设备中的关键电池状态

    公开(公告)号：US20140258698A1

    公开(公告)日：2014-09-11

    申请号：US13791218

    申请日：2013-03-08

    申请人： Ivan Herrera Mejia ,  Kenneth D. Shoemaker ,  Ryan D. Wells

    发明人： Ivan Herrera Mejia ,  Kenneth D. Shoemaker ,  Ryan D. Wells

    IPC分类号： G06F1/28 ,  G06F9/44

    CPC分类号： G06F1/28 ,  G06F1/30 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/00

    摘要： An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen.

    摘要翻译： 诸如SoC的集成电路可以指示关键的电池状态，而不需要在包括主机处理核心的实质部分上供电。 SoC可以包括微控制器，其可以使得临界电池状态数据被存储在静态存储器中，并且显示单元可以从静态存储器检索这样的数据，以在屏幕上显示视觉符号。 SoC的其他部分，例如动态存储器，系统代理，媒体处理器和存储器控制器集线器可以被关闭，而临界电池状态以视觉形式显示在屏幕上。

    Multiple segment register use with different operand size
    8.
    发明授权
    Multiple segment register use with different operand size 有权

    公开(公告)号：US6055652A

    公开(公告)日：2000-04-25

    申请号：US314439

    申请日：1999-05-19

    申请人： Nazar A. Zaidi ,  Kenneth D. Shoemaker ,  Gary N. Hammond

    发明人： Nazar A. Zaidi ,  Kenneth D. Shoemaker ,  Gary N. Hammond

    IPC分类号： G06F12/14 ,  G06F11/16

    CPC分类号： G06F12/1441

    摘要： A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possible address within the segment for each size of memory access. During a subsequent memory access, the limit corresponding to the segment being accessed and the length of memory access is selected. The selected limit is compared against the address of the memory access to determine if a limit violation has occurred. If a limit violation has occurred, a flag is set that, when read, will cause an exception.

    Method and apparatus to limit current-change induced voltage changes in a microcircuit
    9.
    发明授权
    Method and apparatus to limit current-change induced voltage changes in a microcircuit 失效
    限制微电路中电流变化感应电压变化的方法和装置

    公开(公告)号：US07685451B2

    公开(公告)日：2010-03-23

    申请号：US10327441

    申请日：2002-12-20

    申请人： James S. Burns ,  Kenneth D. Shoemaker ,  Sudarshan Kumar ,  Tom E. Wang ,  David J. Ayers ,  Vivek Tiwari

    发明人： James S. Burns ,  Kenneth D. Shoemaker ,  Sudarshan Kumar ,  Tom E. Wang ,  David J. Ayers ,  Vivek Tiwari

    IPC分类号： G06F1/26

    CPC分类号： G06F1/305

    摘要： A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

    摘要翻译： 公开了一种用于补偿电流变化感应电压变化的方法和装置。 在一个实施例中，耦合到指令流水线的数字节流单元可以生成补偿电流信号，然后可以使虚拟负载消耗补偿电流。 在另一个实施例中，响应于时钟频率变化的计数器可产生斜坡电流信号，然后可以使虚拟负载消耗对应于斜坡电流信号的电流。

    High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle
    10.
    发明授权
    High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle 有权
    多线程处理器中的高指令提取带宽使用临时指令高速缓存在随后的时钟周期内传送部分高速缓存行

    公开(公告)号：US06898694B2

    公开(公告)日：2005-05-24

    申请号：US09896346

    申请日：2001-06-28

    申请人： Sailesh Kottapalli ,  James S. Burns ,  Kenneth D. Shoemaker

    发明人： Sailesh Kottapalli ,  James S. Burns ,  Kenneth D. Shoemaker

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48

    CPC分类号： G06F9/3806 ,  G06F9/3802 ,  G06F9/3851

    摘要： The present invention provides a mechanism for supporting high bandwidth instruction fetching in a multi-threaded processor. A multi-threaded processor includes an instruction cache (I-cache) and a temporary instruction cache (TIC). In response to an instruction pointer (IP) of a first thread hitting in the I-cache, a first block of instructions for the thread is provided to an instruction buffer and a second block of instructions for the thread are provided to the TIC. On a subsequent clock interval, the second block of instructions is provided to the instruction buffer, and first and second blocks of instructions from a second thread are loaded into a second instruction buffer and the TIC, respectively.

    摘要翻译： 本发明提供一种用于在多线程处理器中支持高带宽指令提取的机制。 多线程处理器包括指令高速缓存（I-cache）和临时指令高速缓存（TIC）。 响应于在I缓存中击中的第一线程的指令指针（IP），将线程的第一指令块提供给指令缓冲器，并且向TIC提供用于线程的第二指令块。 在随后的时钟间隔中，第二指令块被提供给指令缓冲器，并且来自第二线程的第一和第二指令块分别被加载到第二指令缓冲器和TIC中。