公开(公告)号：US4399890A

公开(公告)日：1983-08-23

申请号：US265407

申请日：1981-05-20

申请人： Leroy R. Bartels ,  John H. Lawson ,  Paul L. King

发明人： Leroy R. Bartels ,  John H. Lawson ,  Paul L. King

IPC分类号： A62B35/04 ,  E06C7/18 ,  A62B1/20

CPC分类号： E06C7/186 ,  A62B35/005 ,  A62B35/0068 ,  A62B35/04

摘要： A flexible cable safety system for a fixed ladder is mounted adjacent to and independent of the ladder. This arrangement is useful for ladders which are not designed to withstand the loads imposed when a safety system arrests the fall of a workman.

摘要翻译： 固定梯子的柔性电缆安全系统安装在梯子附近并独立于梯子。 这种安排对于不能承受安全系统阻止工人跌倒时施加的载荷的梯子是有用的。

公开(公告)号：US07064067B1

公开(公告)日：2006-06-20

申请号：US10770905

申请日：2004-02-02

申请人： Paul L. King ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Minh Van Ngo

发明人： Paul L. King ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Minh Van Ngo

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在栅极周围形成侧壁间隔物。 在半导体衬底中形成源极/漏极结。 在源极/漏极区域和栅极上形成中间相硅化物。 去除侧壁间隔物。 由中间相硅化物形成最终相硅化物。 在半导体衬底上沉积层间电介质，然后在层间电介质中形成接触到最终相硅化物。

公开(公告)号：US06784506B2

公开(公告)日：2004-08-31

申请号：US09939744

申请日：2001-08-28

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L2976

CPC分类号： H01L29/4933 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665

摘要： A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide.

摘要翻译： 通过使用镍作为硅化物的金属成分，在栅电极形成金属硅化物期间防止栅电极的高K电介质层的热分解的方法。

公开(公告)号：US06610181B1

公开(公告)日：2003-08-26

申请号：US09845952

申请日：2001-04-30

申请人： Paul R. Besser ,  Paul L. King ,  Susan Kim

发明人： Paul R. Besser ,  Paul L. King ,  Susan Kim

IPC分类号： C23C1434

CPC分类号： C23C14/545 ,  C23C8/00 ,  C23C16/52 ,  C23C26/00

摘要： The present invention is directed to a method of controlling the formation of metal layers. In one illustrative embodiment, the method comprises depositing a layer of metal above a structure, irradiating at least one area of the layer of metal, and analyzing an x-ray spectrum of x-rays leaving the irradiated area to determine a thickness of the layer of metal. In further embodiments of the present invention, a plurality of areas, and in some cases at least five areas, of the layer of metal are irradiated. The layer of metal may be comprised of, for example, titanium, cobalt, nickel, copper, tantalum, etc.

摘要翻译： 本发明涉及一种控制金属层形成的方法。 在一个说明性实施例中，该方法包括在结构上沉积金属层，照射金属层的至少一个区域，并分析离开照射区域的x射线的X射线光谱，以确定层的厚度 的金属。 在本发明的另外的实施例中，照射金属层的多个区域，并且在一些情况下至少五个区域。 金属层可以由例如钛，钴，镍，铜，钽等组成。

公开(公告)号：US06717236B1

公开(公告)日：2004-04-06

申请号：US10084563

申请日：2002-02-26

申请人： Sergey Lopatin ,  Alexander H. Nickel ,  Paul L. King

发明人： Sergey Lopatin ,  Alexander H. Nickel ,  Paul L. King

IPC分类号： H01L27082

CPC分类号： H01L21/2885 ,  C25D3/58 ,  C25D7/123 ,  C25D17/001 ,  H01L21/76877

摘要： A method of reducing electromigration in a dual-inlaid copper interconnect line (3) by filling a via (6) with a Cu-rich Cu—Zn alloy (30) electroplated on a Cu surface (200 from a stable chemical solution, and by controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a reduced-oxygen Cu—Zn alloy as fill (30) for the via (6) in forming the dual-inlaid interconnect structure (35). The alloy fill (30) is formed by electroplating the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the fill (30) on the Cu surface (20); and annealing the electroplated Cu—Zn alloy fill (30); and planarizing the Cu—Zn alloy fill (30), thereby forming the dual-inlaid copper interconnect line (35).

摘要翻译： 通过在铜表面（200来自稳定的化学溶液和由稳定的化学溶液以及电解质的方式）电镀Cu富Cu Cu-Zn合金（30）填充通孔（6）来减少双镶嵌铜互连线（3）中的电迁移的方法 控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性，以及由此形成的半导体器件，该方法包括使用还原氧Cu-Zn合金作为通孔（6）的填充物（30），形成双重 所述合金填充物（30）通过以包含Zn和Cu的盐的独特的化学溶液，它们的络合剂，pH调节剂和表面活性剂电镀Cu表面（20）而形成，由此电镀 在Cu表面（20）上填充（30）;对电镀的Cu-Zn合金填料（30）进行退火;以及平坦化Cu-Zn合金填料（30），由此形成双嵌入铜互连线（35）。

公开(公告)号：US06559051B1

公开(公告)日：2003-05-06

申请号：US09679881

申请日：2000-10-05

申请人： Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xang

发明人： Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xang

IPC分类号： H01L2144

CPC分类号： H01L21/28194 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66583

摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

摘要翻译： 通过无电镀法形成高质量电介质层，例如由至少一种耐火材料或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作叠层金属栅极MOS晶体管和CMOS器件中的栅极绝缘体层 金属或金属基电介质前体层，其在硅基半导体衬底上包含至少一种难熔或镧系过渡金属，例如Zr和/或Hf，然后使前体层与氧或氧与Si反应 的半导体衬底以形成至少一种金属氧化物或硅酸盐。 本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成 绝缘子接口。

公开(公告)号：US06469387B1

公开(公告)日：2002-10-22

申请号：US09728314

申请日：2000-11-30

申请人： Sergey Lopatin ,  Joffre F. Bernard ,  Paul L. King

发明人： Sergey Lopatin ,  Joffre F. Bernard ,  Paul L. King

IPC分类号： H01L2348

CPC分类号： H01L21/7685 ,  H01L21/288 ,  H01L21/76862 ,  H01L21/76864 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device having contaminant-reduced Ca-doped Cu surfaces formed on Cu interconnects by cost-effectively depositing a Cu—Ca—X surface and subsequently removing the contaminant layer contained therein; and a device thereby formed. In the Cu—Ca—X surface, where contaminant X=C, S, and O, removal of the contaminant from such surface is achieved by (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Cu—Ca—X surface under vacuum onto the underlying Cu interconnect material to form a Cu—Ca film on Cu interconnect structure, thereby producing a uniform Cu—Ca film (i.e., Cu-rich with 0.2-5% Ca) on the Cu surface of an interconnect for maximizing Ca—Cu/Cu interconnect structure reliability, electromigration resistance, and corrosion prevention. The annealing step primarily removes O and secondarily removes C and S, especially when performed under vacuum, an inert gas, or a reducing ambient such as ammonia (NH3) plasma. Thus, the resultant device then comprises a distinctive contaminant-reduced Ca—Cu/Cu interconnect structure.

摘要翻译： 通过成本有效地沉积Cu-Ca-X表面并随后除去其中包含的污染物层，制造在Cu互连上形成的具有污染减少的Ca掺杂的Cu表面的半导体器件的方法; 和由此形成的装置。 在污染物X = C，S和O的Cu-Ca-X表面中，通过（a）将Cu互连表面浸入包含Cu盐，Ca盐， 它们的络合剂，还原剂，pH调节剂和用于促进Cu互连材料的Ca掺杂的至少一种表面活性剂; （b）将Cu-Ca-X表面在真空下退火到下面的Cu互连材料上，以在Cu互连结构上形成Cu-Ca膜，从而产生均匀的Cu-Ca膜（即富含Cu- 5％Ca）在铜互连的Cu表面，以最大限度地提高Ca-Cu / Cu互连结构的可靠性，抗电迁移和防腐蚀。 退火步骤主要去除O，并且二次除去C和S，特别是在真空，惰性气体或还原环境如氨（NH 3）等离子体下进行时）。 因此，所得到的器件然后包括不同的污染物减少的Ca-Cu / Cu互连结构。

公开(公告)号：US06444580B1

公开(公告)日：2002-09-03

申请号：US09728312

申请日：2000-11-30

申请人： Sergey Lopatin ,  Paul L. King ,  Joffre F. Bernard

发明人： Sergey Lopatin ,  Paul L. King ,  Joffre F. Bernard

IPC分类号： H01L2144

CPC分类号： H01L21/7685 ,  H01L21/288 ,  H01L21/76838 ,  H01L21/76862 ,  H01L21/76864 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device having contaminant-reduced calcium-copper (Ca—Cu) alloy surfaces formed on Cu interconnects by cost-effectively removing the contaminant layer and a device thereby formed. Contaminant removal from a Cu—Ca—X surface, where contaminant X=C, S, or O, is achieved by sputtering the Cu—Ca—X surface in an argon (Ar) atmosphere between the steps of (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Ca—Cu alloy surface onto the underlying Cu interconnect material to form a Ca—Cu/Cu interconnect structure, whereby the sputtering step, under Ar, selectively and effectively removes contaminants from the Cu—Ca—X layer containing higher concentrations of C, S, or O, thereby minimizing the post-annealed contaminant level, and thereby producing a uniform Ca—Cu alloy surface (i.e., Cu-rich with 0.2-5% Ca) on the Cu interconnect material for maximizing Ca—Cu/Cu interconnect structure reliability, electromigration resistance, and corrosion prevention. The annealing step primarily removes O and secondarily removes C and S, especially when performed under vacuum, an inert gas, or a reducing ambient such as ammonia (NH3) plasma. Thus, the resultant device then comprises a distinctive contaminant-reduced Ca—Cu/Cu interconnect structure.

摘要翻译： 通过成本有效地去除污染物层和由此形成的器件，制造在Cu互连上形成的具有污染物降低的钙 - 铜（Ca-Cu）合金表面的半导体器件的方法。 污染物X = C，S或O的Cu-Ca-X表面的污染物去除是通过在氩（Ar）气氛中溅射Cu-Ca-X表面，在（a）浸渍Cu 将互连表面连接成包含Cu盐，Ca盐，它们的络合剂，还原剂，pH调节剂和至少一种用于促进Cu互连材料的Ca掺杂的表面活性剂的化学镀溶液; 和（b）将Ca-Cu合金表面退火到下面的Cu互连材料上以形成Ca-Cu / Cu互连结构，由此在Ar下的溅射步骤选择性且有效地从Cu-Ca-X层去除污染物 含有较高浓度的C，S或O，从而使退火后的污染物水平最小化，从而在Cu互连材料上产生均匀的Ca-Cu合金表面（即，具有0.2-5％Ca的富含Cu的Cu），以使 Ca-Cu / Cu互连结构的可靠性，电迁移性和防腐蚀性。 退火步骤主要去除O，并且二次除去C和S，特别是在真空，惰性气体或还原环境如氨（NH 3）等离子体下进行时）。 因此，所得到的器件然后包括不同的污染物减少的Ca-Cu / Cu互连结构。

公开(公告)号：US06380057B1

公开(公告)日：2002-04-30

申请号：US09781225

申请日：2001-02-13

申请人： Matthew S. Buynoski ,  George Jonathan Kluth ,  Paul R. Besser ,  Paul L. King

发明人： Matthew S. Buynoski ,  George Jonathan Kluth ,  Paul R. Besser ,  Paul L. King

IPC分类号： H01L213205

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/28518

摘要： Nickel salicide processing is implemented by implanting nickel into the active regions, prior to depositing Ni, to catalyze the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without the formation of rough interfaces between the nickel silicide layers and underlying silicon and without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions, particularly in the presence of silicon nitride sidewall spacers.

摘要翻译： 镍自杀化处理通过在沉积Ni之前将镍注入活性区域来实现，以在退火期间催化Ni和Si的反应，以在多晶硅栅极电极和源极/漏极区域上形成NiSi层，而不形成在 硅化镍层和底层硅，并且在栅电极上的金属硅化物层与相关源极/漏极区域上的金属硅化物层之间没有导电桥接，特别是在存在氮化硅侧壁间隔物的情况下。

公开(公告)号：US06630741B1

公开(公告)日：2003-10-07

申请号：US10016645

申请日：2001-12-07

申请人： Sergey Lopatin ,  Paul L. King ,  Joffre F. Bernard

发明人： Sergey Lopatin ,  Paul L. King ,  Joffre F. Bernard

IPC分类号： H01L2352

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of reducing electromigration in a graded reduced-oxygen dual-inlaid copper interconnect line by filling a via with a graded Cu-rich Cu—Zn alloy fill electroplated on a Cu surface using a stable chemical solution, and by controlling and ordering the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a graded reduced-oxygen Cu—Zn alloy as fill for the via in forming the dual-inlaid interconnect structure. The graded alloy fill is formed by electroplating, while varying electroplating parameters, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the graded fill on the Cu surface; and annealing the electroplated graded Cu—Zn alloy fill; and planarizing the Cu—Zn alloy fill, thereby forming the graded reduced-oxygen dual-inlaid copper interconnect line.

摘要翻译： 通过使用稳定的化学溶液电镀在Cu表面上的分级富Cu Cu-Zn合金填充通孔，并且通过控制和排序Zn来减少分级的还原氧双嵌入铜互连线中的电迁移的方法 并且还提高了互连可靠性和耐腐蚀性，并且由此形成了半导体器件。 该方法包括在形成双镶嵌互连结构中使用渐变的还原氧Cu-Zn合金作为通孔的填充物。 分级合金填充是通过电镀而形成的，而不同的电镀参数，Cu表面在独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂中，从而将分级填料电镀在Cu表面上; 并对电镀分级的Cu-Zn合金填料进行退火; 并且对Cu-Zn合金填充物进行平坦化，从而形成分级的还原氧双嵌入铜互连线。