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    Process for forming a component insulator on a silicon substrate
    1.
    发明授权
    Process for forming a component insulator on a silicon substrate 失效
    在硅衬底上形成部件绝缘体的工艺

    公开(公告)号：US5110755A

    公开(公告)日：1992-05-05

    申请号：US460703

    申请日：1990-01-04

    申请人： Li-Shu Chen ,  Rathindra N. Ghoshtagore ,  Alfred P. Turley ,  Louis A. Yannone

    发明人： Li-Shu Chen ,  Rathindra N. Ghoshtagore ,  Alfred P. Turley ,  Louis A. Yannone

    IPC分类号： H01L21/306 ,  H01L21/762

    CPC分类号： H01L21/76264 ,  H01L21/306 ,  H01L21/7627

    摘要： A process for forming an insulating layer of silicon dioxide in a silicon substrate that surrounds and electrically insulates a semiconductor device is disclosed herein. The process comprises the steps of forming a recess on the outer surface of the silicon substrate that encompasses the site of the semiconductor device by photo-resist patterned reactive ion etching, and then removing silicon on the surface of the resulting recess whose crystal structure has been damaged by the reactive ion etching. Next, dopant atoms are selectively deposited on the surface of the recess so that the surface of the recess might be rendered into a porous layer of silicon when immersed in hydrogen fluoride and subjected to an electrical current. Prior to the porousification step, silicon is epitaxially grown within the walls of the recess to form the site for a semiconductor device. The substrate is then immersed in hydrogen fluoride while a current is conducted through it in order to porousify the silicon between the device island and the rest of the substrate. Finally, the substrate is thermally oxidized in order to render the porous layer of silicon into a insulating layer of silicon dioxide. The provision of such individual insulating layers around each of the devices on the substrate allows the manufacture of a high density and radiation hard semiconductor array that is not susceptible to electrical current leakage between components.

    摘要翻译： 本文公开了一种在半导体器件中包围并电绝缘的硅衬底中形成二氧化硅绝缘层的工艺。 该方法包括以下步骤：在硅衬底的外表面上形成通过光致抗蚀剂图案化反应离子蚀刻包围半导体器件的位置的凹槽，然后在晶体结构已经形成的凹槽的表面上除去硅 被反应离子蚀刻损坏。 接下来，掺杂剂原子被选择性地沉积在凹部的表面上，使得当浸入氟化氢中并且经受电流时，凹槽的表面可能变成多孔硅层。 在多孔化步骤之前，在凹槽的壁内外延生长硅以形成半导体器件的部位。 然后将衬底浸入氟化氢中，同时通过电流进行电流以使器件岛和衬底的其余部分之间的硅多孔化。 最后，将基底热氧化，以使硅的多孔层成为二氧化硅的绝缘层。 在衬底上的每个器件周围提供这些单独的绝缘层允许制造不易受组件之间的电流泄漏敏感的高密度和辐射硬的半导体阵列。

    Method of making transparent polysilicon gate for imaging arrays
    3.
    发明授权
    Method of making transparent polysilicon gate for imaging arrays 失效
    制造用于成像阵列的透明多晶硅栅极的方法

    公开(公告)号：US5369040A

    公开(公告)日：1994-11-29

    申请号：US58629

    申请日：1993-04-12

    申请人： James Halvis ,  Nathan Bluzer ,  Robert R. Shiskowski ,  Li-Shu Chen

    发明人： James Halvis ,  Nathan Bluzer ,  Robert R. Shiskowski ,  Li-Shu Chen

    IPC分类号： H01L21/8234 ,  H01L31/18

    CPC分类号： H01L21/823406

    摘要： An improved MOS photodetector having polysilicon gate material which is made more transparent to visible light by the addition of up to 50% carbon, and preferably about 10% carbon. The surfaces of the polysilicon-carbon gates are oxidized to form a silicon dioxide dielectric layer, thus eliminating the need to deposit a separate dielectric layer for isolation of adjacent gates in an overlapping gate array. The elimination of a separate dielectric layer permits all gates to be formed directly on the substrate dielectric layer, thus providing a uniform drive voltage requirement across the array.

    摘要翻译： 一种具有多晶硅栅极材料的改进的MOS光电探测器，其通过加入高达50％的碳，优选约10％的碳使得对可见光更透明。 多晶硅 - 碳栅极的表面被氧化形成二氧化硅电介质层，从而消除了在重叠栅极阵列中隔离相邻栅极的单独介电层的需要。 消除单独的电介质层允许所有栅极直接形成在衬底介质层上，从而在整个阵列上提供均匀的驱动电压要求。

    Method of making a self aligned ion implanted gate and guard ring structure for use in a sit
    4.
    发明授权
    Method of making a self aligned ion implanted gate and guard ring structure for use in a sit 有权
    制造自对准离子植入门和保护环结构的方法用于坐着

    公开(公告)号：US07547586B2

    公开(公告)日：2009-06-16

    申请号：US11445215

    申请日：2006-06-02

    申请人： Li-Shu Chen

    发明人： Li-Shu Chen

    IPC分类号： H01L21/332

    CPC分类号： H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7722

    摘要： A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor. A greater separation between a source and gate is obtained by placing a spacer layer on the sidewalls of the pillars, either before or after formation of the skirt.

    摘要翻译： 制造用于静态感应晶体管的半导体结构的方法。 三层SiC材料在基材上，顶层被厚氧化物覆盖。 具有多个条带的掩模沉积在氧化物的顶部以保护其下面的区域，并且蚀刻去除氧化物，第三层和少量的第二层，留下多个柱。 氧化步骤在每个柱的基部周围生长氧化物裙部，并且消耗氧化物下方的第三层的边缘部分以形成源。 离子注入在裙边之间形成门区。 同时，形成多个保护环。 去除所有氧化物导致可以使源极，栅极和漏极连接形成静电感应晶体管的半导体结构。 通过在裙部的形成之前或之后将间隔层放置在柱的侧壁上来获得源极和栅极之间的更大间隔。

    Self-aligned gate fabrication process for silicon carbide static induction transistors
    5.
    发明授权
    Self-aligned gate fabrication process for silicon carbide static induction transistors 失效
    碳化硅静电感应晶体管的自对准栅极制造工艺

    公开(公告)号：US5807773A

    公开(公告)日：1998-09-15

    申请号：US688587

    申请日：1996-07-30

    申请人： Li-Shu Chen ,  Rowland C. Clarke ,  Richard R. Siergiej

    发明人： Li-Shu Chen ,  Rowland C. Clarke ,  Richard R. Siergiej

    IPC分类号： H01L21/04 ,  H01L21/337

    CPC分类号： H01L29/66068 ,  Y10S438/931

    摘要： A method of aligning a gate and a source of a silicon carbide static induction transistor comprising the steps of depositing an oxide layer over the transistor, forming oxide spacers from the oxide layer where the oxide spacers are adjacent the source, depositing a metal layer over the transistor and removing the oxide spacers so that the resulting gates are accurately aligned with the source.

    摘要翻译： 一种对准碳化硅静电感应晶体管的栅极和源极的方法，包括以下步骤：在所述晶体管上沉积氧化物层，从所述氧化物层形成氧化物间隔物，其中所述氧化物间隔物邻近所述源，在所述氧化物层上沉积金属层 去除氧化物间隔物，使得所得到的栅极与源极准确对准。

    Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage
    7.
    发明授权
    Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage 有权
    用于具有改善的栅极至漏极击穿电压的静态感应晶体管中的半导体结构

    公开(公告)号：US07372087B2

    公开(公告)日：2008-05-13

    申请号：US11444497

    申请日：2006-06-01

    申请人： Li-Shu Chen ,  Victor Veliadis

    发明人： Li-Shu Chen ,  Victor Veliadis

    IPC分类号： H01L29/80

    CPC分类号： H01L29/0661 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7722 ,  Y10S438/931

    摘要： A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration of the first layer. A plurality of sources are located on the second layer. A plurality of gates are ion implanted in the second layer, an end one of the gates being connected to all of the plurality of gates and constituting a gate bus. The gate bus has an extension connecting the gate bus in the second layer of higher dopant concentration to the first layer of lower dopant concentration. The extension is ion implanted in either a series of steps or a sloping surface which is formed in the first and second layers.

    摘要翻译： 用于静电感应晶体管的结构包括在衬底上具有第一和第二半导体层的半导体本体，其中第二层的掺杂剂浓度比第一层的掺杂剂浓度高大约一个数量级。 多个源位于第二层上。 在第二层中离子注入多个栅极，门的端部连接到所有多个栅极并构成栅极总线。 栅极总线具有将第二层较高掺杂剂浓度的栅极总线连接到较低掺杂剂浓度的第一层的延伸。 该延伸部以一系列步骤离子注入，或者形成在第一层和第二层中的倾斜表面。

    Capacitive type microelectromechanical RF switch
    8.
    发明授权
    Capacitive type microelectromechanical RF switch 有权
    电容型微机电RF开关

    公开(公告)号：US06777765B2

    公开(公告)日：2004-08-17

    申请号：US10322728

    申请日：2002-12-19

    申请人： Li-Shu Chen ,  Howard N. Fudem ,  Donald E. Crockett ,  Philip C. Smith

    发明人： Li-Shu Chen ,  Howard N. Fudem ,  Donald E. Crockett ,  Philip C. Smith

    IPC分类号： H01L2982

    CPC分类号： H01H59/0009

    摘要： A capacitive type MEMS switch having a conductor arrangement comprised of first and second RF conductors deposited on a substrate. A bridge member having a central enlarged portion is positioned over the conductor arrangement. In one embodiment, the first RF conductor has an end defining an open area in which is positioned a pull down electrode, with the end of the first RF conductor substantially surrounding the pull down electrode. In another embodiment, two opposed RF conductors, each having ends with first and second branches, define an open area in which a pull down electrode is positioned. A dielectric layer is deposited on the conductor arrangement such that when a pull down voltage is applied to the pull down electrode, the switch impedance is significantly reduced so as to allow signal propagation between the RF conductors.

    摘要翻译： 一种电容型MEMS开关，其具有由沉积在基板上的第一和第二RF导体构成的导体装置。 具有中央扩大部分的桥接件位于导体装置的上方。 在一个实施例中，第一RF导体具有限定开放区域的端部，其中定位有下拉电极，第一RF导体的端部基本上围绕下拉电极。 在另一个实施例中，每个具有第一和第二分支的端部的两个相对的RF导体限定其中定位有下拉电极的开放区域。 电介质层沉积在导体布置上，使得当下拉电压施加到下拉电极时，开关阻抗显着减小，以便允许RF导体之间的信号传播。

    Systems and methods for maximizing breakdown voltage in semiconductor devices
    9.
    发明授权
    Systems and methods for maximizing breakdown voltage in semiconductor devices 有权
    用于最大化半导体器件中的击穿电压的系统和方法

    公开(公告)号：US07667242B1

    公开(公告)日：2010-02-23

    申请号：US11601064

    申请日：2006-11-17

    申请人： John V. Veliadis ,  Eric Jonathan Stewart ,  Megan Jean McCoy ,  Li-Shu Chen ,  Ty Richard McNutt

    发明人： John V. Veliadis ,  Eric Jonathan Stewart ,  Megan Jean McCoy ,  Li-Shu Chen ,  Ty Richard McNutt

    IPC分类号： H01L29/74

    CPC分类号： H01L21/76885 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66416

    摘要： Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.

    摘要翻译： 描述了用于最大化半导体器件的击穿电压的系统和方法。 在多重浮动保护环设计中，两个连续组的浮动保护环之间的间隔可以随其与主结的距离而增加，同时保持耗尽区重叠，从而减轻拥挤并最佳地扩展电场，导致击穿电压接近 到本质限制。 在另一个示例性实施例中，与形成另一半导体特征同时制造浮动保护环允许第一浮动保护环相对于主结的边缘精确定位，以及漂浮保护环宽度和间隔的精确控制。 在另一示例性实施例中，半导体器件的掺杂区域之间的垂直间隔的设计调节器件的栅极至源极击穿电压，而不会影响器件的截止电压。