公开(公告)号：US08264021B2

公开(公告)日：2012-09-11

申请号：US12761686

申请日：2010-04-16

申请人： Li-Shyue Lai ,  Tsz-Mei Kwok ,  Chih Chieh Yeh ,  Clement Hsingjen Wann

发明人： Li-Shyue Lai ,  Tsz-Mei Kwok ,  Chih Chieh Yeh ,  Clement Hsingjen Wann

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure.

摘要翻译： Fin场效应晶体管（FinFET）包括在衬底上的鳍状沟道体。 栅电极设置在翅片通道体的上方。 至少一个源极/漏极（S / D）区域邻近鳍状物通道本体设置。 所述至少一个S / D区域基本上不包括任何鳍结构。

公开(公告)号：US08796788B2

公开(公告)日：2014-08-05

申请号：US13009322

申请日：2011-01-19

申请人： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin

发明人： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin

IPC分类号： H01L29/772

CPC分类号： H01L29/6659 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供了用于在半导体器件中形成改进的源极/漏极特征的处理。 具有改善的源极/漏极特征的半导体器件可以防止或减少缺陷并实现由epi层产生的高应变效应。 在一个实施例中，源极/漏极特征包括围绕第一部分的第二部分和在第二部分和半导体衬底之间的第三部分，其中第二部分具有不同于第一和第三部分的组成。

公开(公告)号：US08343872B2

公开(公告)日：2013-01-01

申请号：US12613714

申请日：2009-11-06

申请人： Hsueh-Chang Sung ,  Hsien-Hsin Lin ,  Kuan-Yu Chen ,  Chien-Chang Su ,  Tsz-Mei Kwok ,  Yi-Fang Pai

发明人： Hsueh-Chang Sung ,  Hsien-Hsin Lin ,  Kuan-Yu Chen ,  Chien-Chang Su ,  Tsz-Mei Kwok ,  Yi-Fang Pai

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

摘要： The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material.

摘要翻译： 本公开提供了一种制造方法，包括提供半导体衬底; 在基板上形成栅极结构; 执行注入工艺以在所述衬底中形成掺杂区域; 在所述栅极结构的侧壁上形成间隔物; 执行第一蚀刻以在所述衬底中形成凹部，其中所述第一蚀刻去除所述掺杂区域的一部分; 执行第二蚀刻以扩大基板中的凹部，其中第二蚀刻包括蚀刻剂和提高在掺杂区域的剩余部分处的蚀刻速率的催化剂; 并用半导体材料填充凹部。

公开(公告)号：US20110193141A1

公开(公告)日：2011-08-11

申请号：US12703918

申请日：2010-02-11

申请人： Hsien-Hsin Lin ,  Tsz-Mei Kwok ,  Chien-Chang Su

发明人： Hsien-Hsin Lin ,  Tsz-Mei Kwok ,  Chien-Chang Su

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation; a fin structure of the crystalline semiconductor material overlying the substrate; a gate structure over a portion of the fin structure; an epitaxy layer over another portion of the fin structure, the epitaxy layer having a surface having a second crystal plane orientation, wherein the epitaxy layer and underlying fin structure include a source and drain region, the source region being separated from the drain region by the gate structure; and a channel defined in the fin structure from the source region to the drain region, and aligned in a direction parallel to both the surface of the epitaxy layer and the top surface of the substrate.

摘要翻译： 公开了一种用于制造FinFET器件的FinFET器件和方法。 示例性的FinFET器件包括具有第一晶面取向的顶表面的晶体半导体材料的衬底; 覆盖衬底的晶体半导体材料的鳍状结构; 翅片结构的一部分上的栅极结构; 在鳍结构的另一部分上的外延层，所述外延层具有具有第二晶面取向的表面，其中所述外延层和下面的鳍结构包括源极和漏极区，源极区与漏极区分离， 门结构; 以及在鳍结构中从源极区域到漏极区域限定的沟道，并且在平行于外延层的表面和衬底的顶表面的方向上排列。

公开(公告)号：US09666691B2

公开(公告)日：2017-05-30

申请号：US13608961

申请日：2012-09-10

申请人： Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

发明人： Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/785

摘要： A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

公开(公告)号：US08835982B2

公开(公告)日：2014-09-16

申请号：US13026519

申请日：2011-02-14

申请人： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin

发明人： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin

IPC分类号： H01L29/72

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66598 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供了在半导体器件中形成改进的轻掺杂源极/漏极特征和源极/漏极特征的处理。 具有改进的轻掺杂源极/漏极特征和源极/漏极特征的半导体器件可以防止或减少缺陷并实现高应变效应。 在至少一个实施例中，轻掺杂源极/漏极特征和源极/漏极特征包括通过外延生长形成的相同的半导体材料。

公开(公告)号：US08674453B2

公开(公告)日：2014-03-18

申请号：US13324331

申请日：2011-12-13

申请人： Chun Hsiung Tsai ,  Tsan-Chun Wang ,  Su-Hao Liu ,  Tsz-Mei Kwok ,  Chii-Meng Wu

发明人： Chun Hsiung Tsai ,  Tsan-Chun Wang ,  Su-Hao Liu ,  Tsz-Mei Kwok ,  Chii-Meng Wu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/22 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/32 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.

摘要翻译： 上述过程和结构的实施例提供了改善载体移动性的机制。 源极和漏极区中的位错以及由晶体管的沟道区旁边的掺杂外延材料产生的应变都有助于沟道区中的应变。 结果，设备性能得到改善。

公开(公告)号：US08362575B2

公开(公告)日：2013-01-29

申请号：US12831925

申请日：2010-07-07

申请人： Tsz-Mei Kwok ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Hsien-Hsin Lin

发明人： Tsz-Mei Kwok ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Hsien-Hsin Lin

IPC分类号： H01L27/088 ,  H01L21/70 ,  H01L21/02 ,  H01L29/06 ,  H01L29/04 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/7851 ,  H01L21/76 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

公开(公告)号：US08310013B2

公开(公告)日：2012-11-13

申请号：US12703918

申请日：2010-02-11

申请人： Hsien-Hsin Lin ,  Tsz-Mei Kwok ,  Chien-Chang Su

发明人： Hsien-Hsin Lin ,  Tsz-Mei Kwok ,  Chien-Chang Su

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation; a fin structure of the crystalline semiconductor material overlying the substrate; a gate structure over a portion of the fin structure; an epitaxy layer over another portion of the fin structure, the epitaxy layer having a surface having a second crystal plane orientation, wherein the epitaxy layer and underlying fin structure include a source and drain region, the source region being separated from the drain region by the gate structure; and a channel defined in the fin structure from the source region to the drain region, and aligned in a direction parallel to both the surface of the epitaxy layer and the top surface of the substrate.

摘要翻译： 公开了一种用于制造FinFET器件的FinFET器件和方法。 示例性的FinFET器件包括具有第一晶面取向的顶表面的晶体半导体材料的衬底; 覆盖衬底的晶体半导体材料的鳍状结构; 翅片结构的一部分上的栅极结构; 在鳍结构的另一部分上的外延层，所述外延层具有具有第二晶面取向的表面，其中所述外延层和下面的鳍结构包括源极和漏极区，源极区与漏极区分离由 门结构; 以及在鳍结构中从源极区域到漏极区域限定的沟道，并且在平行于外延层的表面和衬底的顶表面的方向上排列。

公开(公告)号：US20110210404A1

公开(公告)日：2011-09-01

申请号：US12713573

申请日：2010-02-26

申请人： Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

发明人： Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/785

摘要： A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

摘要翻译： 一种形成集成电路结构的方法包括在衬底的主表面上提供包括衬底和半导体鳍片的晶片，并且执行沉积步骤以在半导体鳍片的顶表面和侧壁上外延生长外延层，其中 外延层包括半导体材料。 然后执行蚀刻步骤以去除外延层的一部分，其中外延层的剩余部分保留在半导体鳍片的顶表面和侧壁上。