公开(公告)号：US08674453B2

公开(公告)日：2014-03-18

申请号：US13324331

申请日：2011-12-13

申请人： Chun Hsiung Tsai ,  Tsan-Chun Wang ,  Su-Hao Liu ,  Tsz-Mei Kwok ,  Chii-Meng Wu

发明人： Chun Hsiung Tsai ,  Tsan-Chun Wang ,  Su-Hao Liu ,  Tsz-Mei Kwok ,  Chii-Meng Wu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/22 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/32 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.

摘要翻译： 上述过程和结构的实施例提供了改善载体移动性的机制。 源极和漏极区中的位错以及由晶体管的沟道区旁边的掺杂外延材料产生的应变都有助于沟道区中的应变。 结果，设备性能得到改善。

公开(公告)号：US08987099B2

公开(公告)日：2015-03-24

申请号：US13332011

申请日：2011-12-20

申请人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Tsan-Chun Wang

发明人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Tsan-Chun Wang

IPC分类号： H01L21/336 ,  H01L21/268 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/2686 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

摘要： The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

摘要翻译： 本公开提供了在一个实施例中制造集成电路的方法。 该方法包括提供具有有源区的半导体衬底和设置在有源区中的半导体衬底上的第一栅叠层; 在所述半导体衬底上形成原位磷掺杂碳化硅（SiCP）特征并且设置在所述第一栅极叠层的侧面上; 用具有高k介电材料层的第二栅极堆叠代替第一栅极堆叠; 然后进行具有第一热小波和第二热小波的热分布的毫秒退火（MSA）处理。

公开(公告)号：US20130157431A1

公开(公告)日：2013-06-20

申请号：US13332011

申请日：2011-12-20

申请人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Tsan-Chun Wang

发明人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Tsan-Chun Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/2686 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

摘要： The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

摘要翻译： 本公开提供了在一个实施例中制造集成电路的方法。 该方法包括提供具有有源区的半导体衬底和设置在有源区中的半导体衬底上的第一栅叠层; 在所述半导体衬底上形成原位磷掺杂碳化硅（SiCP）特征并且设置在所述第一栅极叠层的侧面上; 用具有高k介电材料层的第二栅极堆叠代替第一栅极堆叠; 然后进行具有第一热小波和第二热小波的热分布的毫秒退火（MSA）处理。

公开(公告)号：US08884341B2

公开(公告)日：2014-11-11

申请号：US13210962

申请日：2011-08-16

申请人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Chien-Tai Chan ,  King-Yuen Wong ,  Chien-Chang Su

发明人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Chien-Tai Chan ,  King-Yuen Wong ,  Chien-Chang Su

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08

CPC分类号： H01L29/7834 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66636

摘要： An integrated circuit includes a gate electrode disposed over a substrate. A source/drain (S/D) region is disposed adjacent to the gate electrode. The S/D region includes a diffusion barrier structure disposed in a recess of the substrate. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode. The second portion is distant from the gate electrode. An N-type doped silicon-containing structure is disposed over the diffusion barrier structure. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. The second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.

摘要翻译： 集成电路包括设置在基板上的栅电极。 源极/漏极（S / D）区域邻近栅电极设置。 S / D区域包括设置在基板的凹部中的扩散阻挡结构。 扩散阻挡结构包括第一部分和第二部分。 第一部分与栅电极相邻。 第二部分远离栅电极。 在扩散阻挡结构上设置N型掺杂的含硅结构。 扩散阻挡结构的第一部分被配置为部分地防止N型掺杂的含硅结构的N型掺杂剂扩散到衬底中。 扩散阻挡结构的第二部分被配置为基本上完全防止N型掺杂含硅结构的N型掺杂剂扩散到衬底中。