公开(公告)号：US06043547A

公开(公告)日：2000-03-28

申请号：US870896

申请日：1997-06-06

申请人： Liang-Choo Hsia ,  Thomas Chang

发明人： Liang-Choo Hsia ,  Thomas Chang

IPC分类号： G03F1/00 ,  G03F7/09 ,  H01L21/027 ,  H01L31/0232 ,  H01L23/48 ,  H01L23/52 ,  H01L23/58

CPC分类号： H01L21/0276 ,  G03F1/46 ,  G03F1/52 ,  G03F7/091 ,  Y10S430/151 ,  Y10S438/952

摘要： An antireflection coating (116) for use in fabricating integrated circuits and electronic devices comprises a film of chromium oxide, CrO, or chromium suboxide, CrO.sub.x where x

摘要翻译： 用于制造集成电路和电子器件的抗反射涂层（116）包括氧化铬，CrO或低氧化铬铬，其中x <1的CrO x。 当施加在高反射层（114）上时，抗反射层减少光致抗蚀剂层（118）中的驻波和地形凹陷。 高反射层可以是金属，例如铝或金，硅化物或半导体，例如硅。 这些涂层优选通过溅射室中的具有氧的分压的铬靶的反应溅射来制造。 抗反射层主要通过吸收而不是波形匹配原理起作用。 该抗反射层表现出良好的粘附性并且可以集成到该装置中。 将层集成到器件中可以减少下层中的应力并提高器件的产量和可靠性。

公开(公告)号：US6008515A

公开(公告)日：1999-12-28

申请号：US74486

申请日：1998-05-06

申请人： Liang-Choo Hsia ,  Thomas Chang

发明人： Liang-Choo Hsia ,  Thomas Chang

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L28/87 ,  H01L28/88

摘要： A method of forming a capacitor that has improved charge storage capacity in a high density memory device that has shallow trench isolation regions and a capacitor produced by the method are provided. The method includes the step of forming an oxide spacer that consists of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a contact hole is first etched by a plasma etching technique, the hole is again decoratively etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a corrugated side-wall of the contact hole is formed which affords the capacitor cell with an increased surface area leading to an improved charge storage capacity.

摘要翻译： 提供一种形成在具有浅沟槽隔离区域的高密度存储器件中具有改进的电荷存储容量的电容器和通过该方法产生的电容器的方法。 该方法包括形成由通过热CVD和等离子体CVD两种交替方法沉积的多个氧化物层组成的氧化物间隔物的步骤。 在通过等离子体蚀刻技术首先蚀刻接触孔之后，通过诸如氟化氢的蚀刻剂再次装饰性地蚀刻孔，其对通过等离子体CVD法形成的氧化物层具有高选择性，并且对由 热CVD法。 结果，形成接触孔的波纹侧壁，其使电容器单元具有增加的表面积，从而提高电荷存储容量。

公开(公告)号：US5851898A

公开(公告)日：1998-12-22

申请号：US697442

申请日：1996-08-23

申请人： Liang-Choo Hsia ,  Thomas Chang

发明人： Liang-Choo Hsia ,  Thomas Chang

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/31612 ,  H01L28/87 ,  H01L21/76895 ,  H01L28/88

摘要： A method of forming a capacitor that has improved charge storage capability and a capacitor produced by such method are provided. The method utilizes an additional layer of oxide spacer consisting of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a contact hole is first etched by a plasma etching technique, the hole is again etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a corrugated side-wall of the contact hole is formed which affords the capacitor cell with a substantially increased surface area leading to an improved charge storage capability.

摘要翻译： 提供一种形成具有改善的电荷存储能力的电容器的方法和通过这种方法制造的电容器。 该方法利用由通过热CVD和等离子体CVD的两种交替方法沉积的多个氧化物层组成的附加的氧化物间隔层。 在通过等离子体蚀刻技术首先蚀刻接触孔之后，通过诸如氟化氢的蚀刻剂再次蚀刻该孔，其对通过等离子体CVD法形成的氧化物层具有高选择性，并且对由热 CVD法。 结果，形成接触孔的波纹状侧壁，其使电容器单元具有显着增加的表面积，从而提高电荷存储能力。

公开(公告)号：US5789267A

公开(公告)日：1998-08-04

申请号：US702747

申请日：1996-08-23

申请人： Liang-Choo Hsia ,  Thomas Chang

发明人： Liang-Choo Hsia ,  Thomas Chang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87

摘要： A method of forming a cell contact that has improved structural strength and break-down resistance and a cell contact produced by such method are provided. The method utilizes an oxide spacer consisting of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a straight contact opening is first etched by a plasma etching technique, the hole is again etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a contact opening having a corrugated side-wall is formed and into which a polysilicon is deposited to substantially fill the hole. A cell contact having a corrugated side-wall configuration is thus formed which presents improved structural rigidity and break-down resistance. A layer of rugged polysilicon layer may optionally be deposited before the deposition of the polysilicon into the contact opening to further increase the surface area of the cell contact.

摘要翻译： 提供了一种形成具有改进的结构强度和耐断裂性的电池接触的方法以及通过这种方法制造的电池接触。 该方法利用由通过热CVD和等离子体CVD的两种交替方法沉积的多个氧化物层组成的氧化物间隔物。 在通过等离子体蚀刻技术首先蚀刻直接接触开口之后，再次通过诸如氟化氢的蚀刻剂蚀刻该孔，其对通过等离子体CVD法形成的氧化物层具有高选择性，并且对由 热CVD法。 结果，形成具有波形侧壁的接触开口，并且沉积多晶硅以基本上填充该孔。 由此形成具有波纹状的侧壁结构的电池触点，其具有改善的结构刚性和耐断裂性。 在将多晶硅沉积到接触开口中之前，可以任选地沉积一层坚固的多晶硅层，以进一步增加电池接触的表面积。

公开(公告)号：US5909621A

公开(公告)日：1999-06-01

申请号：US795789

申请日：1997-02-05

申请人： Liang-Choo Hsia ,  Thomas Chang

发明人： Liang-Choo Hsia ,  Thomas Chang

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/87 ,  H01L28/91

摘要： A method of fabricating single-side corrugated cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells. The corrugated capacitor shape is achieved by depositing the thermal chemical vapor deposition (CVD) oxide and the plasma-enhanced CVD (PECVD) oxide alternating layers. Then, the thermal CVD oxide and the PECVD oxide layers are lateral etched by hydrofluoric acid (HF). Because hydrofluoric acid (HF) etches the thermal CVD oxide at a slower rate than etches the PECVD oxide, a cavity (undercut) is formed in each PECVD oxide layer. Therefore, the single-side corrugated shape capacitor surface is created that increases the surface area of the capacitor considerably. The cylindrical capacitor storage node of the DRAM capacitor of this method has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices.

摘要翻译： 一种制造高密度动态随机存取存储器（DRAM）单元的单面波纹圆柱形电容器的方法。 通过沉积热化学气相沉积（CVD）氧化物和等离子体增强CVD（PECVD）氧化物交替层来实现波纹电容器形状。 然后，通过氢氟酸（HF）横向蚀刻热CVD氧化物和PECVD氧化物层。 因为氢氟酸（HF）以比蚀刻PECVD氧化物更慢的速度蚀刻热CVD氧化物，所以在每个PECVD氧化物层中形成空穴（底切）。 因此，产生单侧波纹状电容器表面，从而显着地增加电容器的表面积。 该方法的DRAM电容器的圆柱形电容器存储节点具有大得多的表面积，从而增加DRAM电容器的电容值，从而可以实现集成电路器件的高封装密度。

公开(公告)号：US6162724A

公开(公告)日：2000-12-19

申请号：US59517

申请日：1998-04-13

申请人： Liang-Choo Hsia ,  Thomas Chang

发明人： Liang-Choo Hsia ,  Thomas Chang

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an improved method for forming metalization layers for inter-layer connections including the steps of first providing a substrate, then depositing a metal layer on the substrate, then depositing a dielectric layer overlying the metal layer, etching away an opening in the dielectric layer to expose at least partially the metal layer, and etching an opening in the metal layer by using the dielectric layer as a mask to at least partially expose the underlying substrate. The method may optionally includes the step of blanket depositing a thin oxide layer and then an inter-level dielectric layer on top of the device.

摘要翻译： 本发明提供一种用于形成层间连接的金属化层的改进方法，包括以下步骤：首先提供衬底，然后在衬底上沉积金属层，然后沉积覆盖在金属层上的电介质层，蚀刻掉 电介质层以至少部分地暴露金属层，并且通过使用电介质层作为掩模蚀刻金属层中的开口以至少部分地暴露下面的衬底。 该方法可以可选地包括以下步骤：在器件的顶部上覆盖薄的氧化物层，然后是层间介电层。

公开(公告)号：US5827783A

公开(公告)日：1998-10-27

申请号：US697443

申请日：1996-08-23

申请人： Liang-Choo Hsia ,  Thomas Chang

发明人： Liang-Choo Hsia ,  Thomas Chang

IPC分类号： H01L21/02 ,  H01L21/465

CPC分类号： H01L28/87 ,  H01L28/88

摘要： A method of forming a capacitor that has improved charge storage capacity in a high density memory device that has shallow trench isolation regions and a capacitor produced by the method are provided. The method includes the step of forming an oxide spacer that consists of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a contact hole is first etched by a plasma etching technique, the hole is again decoratively etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a corrugated side-wall of the contact hole is formed which affords the capacitor cell with an increased surface area leading to an improved charge storage capacity.

公开(公告)号：US5701013A

公开(公告)日：1997-12-23

申请号：US660486

申请日：1996-06-07

申请人： Liang-Choo Hsia ,  Thomas Chang

发明人： Liang-Choo Hsia ,  Thomas Chang

IPC分类号： G03F7/20 ,  H01J37/20 ,  H01L23/544 ,  H01J37/304

CPC分类号： G01Q40/02 ,  B82Y35/00 ,  G03F7/70625 ,  G03F7/70633 ,  H01L22/34 ,  H01L2223/54453

摘要： The present invention provides a wafer metrology pattern integrating both overlay and critical dimension features for SEM or AFM measurements. The present invention provides an improved test mask target which contains lines measuring 0.25 .mu.m, 0.3 .mu.m, and 0.5 .mu.m. The spaces between the lines can be adjusted accordingly. The improved test mask target provides a pattern that combines the wafer critical dimension and box-in-box overlay targets into a single structure. As a result, the pattern may be used for both overlay and critical dimension verifications in a single AMF or SEM measurement. More precisely, wafer overlay and critical dimension disposition may be made simultaneously, reducing the need to perform multiple measurements at each testing step.

摘要翻译： 本发明提供了集成用于SEM或AFM测量的覆盖和关键尺寸特征的晶片度量图。 本发明提供一种改进的测试掩模靶，其包含测量为0.25μm，0.3μm和0.5μm的线。 线之间的空间可以相应调整。 改进的测试掩模目标提供了将晶圆临界尺寸和盒装叠加目标组合成单个结构的图案。 因此，在单次AMF或SEM测量中，图案可用于覆盖和临界尺寸验证。 更准确地说，可以同时进行晶片覆盖和临界尺寸配置，减少在每个测试步骤执行多个测量的需要。

公开(公告)号：US5843822A

公开(公告)日：1998-12-01

申请号：US796023

申请日：1997-02-05

申请人： Liang-Choo Hsia ,  Thomas Chang

发明人： Liang-Choo Hsia ,  Thomas Chang

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/87 ,  H01L28/91

摘要： A method of fabricating double-side corrugated cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells. The corrugated capacitor shape is achieved by depositing the thermal chemical vapor deposition (CVD) oxide and the plasma-enhanced CVD (PECVD) oxide alternating layers. Then, the thermal CVD oxide and the PECVD oxide layers are vertically etched to form two trenches followed by laterally etched by hydrofluoric acid (HF). Because hydrofluoric acid (HF) etches the thermal CVD oxide at a slower rate than etches the PECVD oxide, a cavity is formed in each PECVD oxide layer along the trenches. Finally, polysilicon layer is deposited filling into the trenches. Therefore, the double-side corrugated shape capacitor surface is created that increases the surface area of the capacitor considerably. The cylindrical capacitor storage node of the DRAM capacitor of this method has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices.

摘要翻译： 一种制造高密度动态随机存取存储器（DRAM）单元的双面波纹圆柱形电容器的方法。 通过沉积热化学气相沉积（CVD）氧化物和等离子体增强CVD（PECVD）氧化物交替层来实现波纹电容器形状。 然后，将热CVD氧化物和PECVD氧化物层垂直蚀刻以形成两个沟槽，随后用氢氟酸（HF）横向蚀刻。 因为氢氟酸（HF）以比刻蚀PECVD氧化物更慢的速度蚀刻热CVD氧化物，所以沿着沟槽在每个PECVD氧化物层中形成空穴。 最后，沉积多晶硅层到沟槽中。 因此，产生增加电容器的表面积的双面波纹状电容器表面。 该方法的DRAM电容器的圆柱形电容器存储节点具有大得多的表面积，从而增加DRAM电容器的电容值，从而可以实现集成电路器件的高封装密度。

公开(公告)号：US5672243A

公开(公告)日：1997-09-30

申请号：US563526

申请日：1995-11-28

申请人： Liang-Choo Hsia ,  Thomas Chang

发明人： Liang-Choo Hsia ,  Thomas Chang

IPC分类号： G03F1/00 ,  G03F7/09 ,  H01L21/027 ,  H01L21/3105

CPC分类号： H01L21/0276 ,  G03F1/46 ,  G03F1/52 ,  G03F7/091 ,  Y10S430/151 ,  Y10S438/952

摘要： An antireflection coating (116) for use in fabricating integrated circuits and electronic devices comprises a film of chromium oxide, CrO, or chromium suboxide, CrO.sub.x where x

摘要翻译： 用于制造集成电路和电子器件的抗反射涂层（116）包括氧化铬，CrO或低氧化铬铬，其中x <1的CrO x。 当施加在高反射层（114）上时，抗反射层减少光致抗蚀剂层（118）中的驻波和地形凹陷。 高反射层可以是金属，例如铝或金，硅化物或半导体，例如硅。 这些涂层优选通过溅射室中的具有氧的分压的铬靶的反应溅射来制造。 抗反射层主要通过吸收而不是波形匹配原理起作用。 该抗反射层表现出良好的粘附性并且可以集成到该装置中。 将层集成到器件中可以减少下层中的应力并提高器件的产量和可靠性。