公开(公告)号：US20080294446A1

公开(公告)日：2008-11-27

申请号：US11805245

申请日：2007-05-22

申请人： Linfeng Guo ,  Hua Zheng ,  Mark Sydorenko ,  Yang Li

发明人： Linfeng Guo ,  Hua Zheng ,  Mark Sydorenko ,  Yang Li

IPC分类号： G10L19/00

CPC分类号： G10L19/167 ,  G10L19/0017 ,  G10L19/0204 ,  G10L19/24

摘要： Source signals, such as audio and/or video data, are encoded into multiple, consecutive frequency bands. These bands are referred to as coding layers. Rather than performing complex bit-slice operations, a disclosed technique enables an agile and simplified response to transmission channel throughput variations. Specifically, if it becomes necessary to restrict the rate of data transmission to avoid receiver buffer underflow resulting from transmission channel degradation, layers from the transmitted signal are omitted, beginning with the highest frequency bands. Efficient and agile bit rate scalability during data streaming through wired or wireless networks and during local playback is thus enabled.

摘要翻译： 诸如音频和/或视频数据的源信号被编码成多个连续的频带。 这些频带被称为编码层。 所公开的技术不是执行复杂的位片操作，而是能够对传输信道吞吐量变化进行敏捷和简化的响应。 具体地，如果需要限制数据传输速率以避免由于传输信道恶化导致的接收机缓冲器下溢，则从最高频带开始，从发送信号中省去层。 因此，通过有线或无线网络和本地播放期间的数据流传输期间，高效且敏捷的比特率可扩展性得以实现。

公开(公告)号：US20070192086A1

公开(公告)日：2007-08-16

申请号：US11352952

申请日：2006-02-13

申请人： Linfeng Guo ,  Yang Li ,  Mark Sydorenko ,  Hua Zheng

发明人： Linfeng Guo ,  Yang Li ,  Mark Sydorenko ,  Hua Zheng

IPC分类号： G10L19/00

CPC分类号： G10L19/16 ,  G10L25/30

摘要： The automatic and optimal selection of coding parameter values according to analyses of coding trials is disclosed. The Neural Encoding Model (NEM) provides a method for providing a quantitative measure of the likelihood that a human observer can distinguish an original sensory signal from an approximation thereof, thus providing a metric by which the effect of various coding parameters may be analyzed and optimized. Optimal coding parameters can be defined for an entire data set, such as a digitized audio file, or for discrete portions of the data set. A trial coded data set or portion thereof is analyzed to determining if certain coding parameters have been assigned optimal values. If not, parameter manipulation is performed in an intelligent order and the objective analysis is repeated until predetermined objective perceptual distance criteria are achieved.

摘要翻译： 公开了根据编码试验分析的编码参数值的自动优化选择。 神经编码模型（NEM）提供了一种方法，用于提供对人类观察者可以区分原始感觉信号与其近似的可能性的定量测量，从而提供可以分析和优化各种编码参数的效果的度量 。 可以为整个数据集（例如数字化音频文件）或数据集的离散部分定义最佳编码参数。 分析试验编码数据集或其部分，以确定某些编码参数是否已被分配最佳值。 如果不是，则以智能顺序执行参数操作，并且重复客观分析，直到达到预定的客观感知距离标准。

公开(公告)号：US20080034026A1

公开(公告)日：2008-02-07

申请号：US11498317

申请日：2006-08-01

申请人： Linfeng Guo ,  Yang Li ,  Mark Sydorenko ,  Jun Tian ,  Hua Zheng

发明人： Linfeng Guo ,  Yang Li ,  Mark Sydorenko ,  Jun Tian ,  Hua Zheng

IPC分类号： G06F17/14 ,  G06F17/10 ,  G06F17/40

CPC分类号： G06F17/142

摘要： A method for improving precision in FFT calculations. For each iteration in an FFT implementation, a constant normalization multiplier is inserted such that the dynamic ranges of the input and output are the same. The final FFT output is multiplied by a constant normalization factor given by the number of iterations and the constant normalization multiplier.

摘要翻译： 一种提高FFT计算精度的方法。 对于FFT实现中的每次迭代，插入常数归一化乘数，使得输入和输出的动态范围相同。 最终FFT输出乘以由迭代次数和常数归一化乘数给出的常数归一化因子。

公开(公告)号：US20080034027A1

公开(公告)日：2008-02-07

申请号：US11498319

申请日：2006-08-01

申请人： Linfeng Guo ,  Yang Li ,  Mark Sydorenko ,  Jun Tian ,  Hua Zheng

发明人： Linfeng Guo ,  Yang Li ,  Mark Sydorenko ,  Jun Tian ,  Hua Zheng

IPC分类号： G06F7/38

CPC分类号： G06F7/49942 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/523

摘要： Round-off error in fixed-point arithmetic is minimized by changing the magnitudes of two multipliers simultaneously. The dynamic range of an intermediate output is thus maximized to increase computation precision. A much smaller round-off error, caused by fixed-point arithmetic, thus results.

摘要翻译： 通过同时改变两个乘法器的幅度来最小化定点运算中的舍入误差。 因此，中间输出的动态范围被最大化以增加计算精度。 因此，由定点算术引起的更小的舍入误差就会导致。

公开(公告)号：US08896640B2

公开(公告)日：2014-11-25

申请号：US13578622

申请日：2012-06-13

申请人： Hua Zheng ,  Cheng-hung Chen

发明人： Hua Zheng ,  Cheng-hung Chen

IPC分类号： G09G5/10

CPC分类号： G09G5/10 ,  G09G3/20 ,  G09G3/2092 ,  G09G2300/0408 ,  G09G2310/0281 ,  G09G2320/0223

摘要： The display panel includes data driven chip and at least two scanning driven chips. The second scanning signal input terminal of each of the scanning driven chip is connected to a first scanning signal output terminal of the data driven chip by corresponding transmission circuits. At least one transmission circuit includes a serially connected resistor so that sum of impedance of the transmission circuits are equal, or the difference of the impedance of the transmission circuit is less than a predetermined value. In addition, a flat-panel display device with uniform brightness and a driving method thereof are also provided.

摘要翻译： 显示面板包括数据驱动芯片和至少两个扫描驱动芯片。 每个扫描驱动芯片的第二扫描信号输入端通过相应的传输电路连接到数据驱动芯片的第一扫描信号输出端。 至少一个传输电路包括串联的电阻器，使得发送电路的阻抗之和相等，或者发送电路的阻抗差小于预定值。 此外，还提供了具有均匀亮度的平板显示装置及其驱动方法。

公开(公告)号：US20120060104A1

公开(公告)日：2012-03-08

申请号：US12876964

申请日：2010-09-07

申请人： Eric I. Feng ,  Hua Zheng ,  Xin Jin ,  Zhibing Wang

发明人： Eric I. Feng ,  Hua Zheng ,  Xin Jin ,  Zhibing Wang

IPC分类号： G06F3/048

CPC分类号： H04L65/403 ,  G06F3/0481 ,  G06F3/0484 ,  G06F3/0487 ,  H04L12/1813 ,  H04N21/4755 ,  H04N21/4788 ,  H04N21/812 ,  H04N21/8133

摘要： A method and apparatus for sharing viewing information is disclosed. In one embodiment, the method comprises receiving an designation of a second user from the first user; and transmitting the first user viewing information to the designated second user. The shared viewing information may comprise the identity of a currently viewed media program, a list of scheduled media program viewings, or the media program itself.

摘要翻译： 公开了一种用于共享观看信息的方法和装置。 在一个实施例中，该方法包括从第一用户接收第二用户的指定; 以及将所述第一用户观看信息发送到所述指定的第二用户。 共享观看信息可以包括当前所查看的媒体节目的标识，预定的媒体节目观看列表或媒体节目本身。

公开(公告)号：US06921827B2

公开(公告)日：2005-07-26

申请号：US10415569

申请日：2001-11-14

申请人： Wayne Douglas Luke ,  Heidi Ann Sanderson ,  Hua Zheng

发明人： Wayne Douglas Luke ,  Heidi Ann Sanderson ,  Hua Zheng

IPC分类号： C07D333/52 ,  C07D333/56 ,  C07D333/64 ,  C07D409/00

CPC分类号： C07D333/64 ,  C07D333/56

摘要： The present invention relates to a process for preparing a compound of formula (I): which includes cyclodehydrating a compound of formula (II): in the presence of an acid activated clay or acid activated zeolite catalyst and in the presence of a suitable solvent

摘要翻译： 本发明涉及一种制备式（I）化合物的方法：其包括将式（II）化合物环状脱水：在酸活化的粘土或酸活化的沸石催化剂存在下，并在合适的溶剂

公开(公告)号：US06756805B2

公开(公告)日：2004-06-29

申请号：US10295499

申请日：2002-11-15

申请人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

发明人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

IPC分类号： G01R104

CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

公开(公告)号：US06512711B1

公开(公告)日：2003-01-28

申请号：US09572820

申请日：2000-05-16

申请人： Jeffrey P. Wright ,  Hua Zheng

发明人： Jeffrey P. Wright ,  Hua Zheng

IPC分类号： G11C700

CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109

摘要： A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

公开(公告)号：US06365421B2

公开(公告)日：2002-04-02

申请号：US09531023

申请日：2000-03-20

申请人： Brett Debenham ,  Kim Pierce ,  Douglas J. Cutter ,  Kurt Beigel ,  Fan Ho ,  Patrick J. Mullarkey ,  Dien Luong ,  Hua Zheng ,  Michael Shore ,  Jeffrey P. Wright ,  Adrian E. Ong ,  Todd A. Merritt

发明人： Brett Debenham ,  Kim Pierce ,  Douglas J. Cutter ,  Kurt Beigel ,  Fan Ho ,  Patrick J. Mullarkey ,  Dien Luong ,  Hua Zheng ,  Michael Shore ,  Jeffrey P. Wright ,  Adrian E. Ong ,  Todd A. Merritt

IPC分类号： H01L2166

CPC分类号： H01L27/112 ,  G01R31/31702 ,  G01R31/3181 ,  G11C17/10 ,  G11C17/18

摘要： An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests associated with the selected point in the process. Prior to performing further tests on the device, the element is read to verify that it passed previous tests in the test process. If the appropriate elements are not programmed, the device is rejected. A rejected device may be retested according to the previous test steps. Laser fuses, electrically programmable fuses or antifuses are used to store test results. The use of electrically writeable nonvolatile memory elements allows for programming of the elements after the device has been packaged.

摘要翻译： 集成电路存储器件具有多个非易失性可编程元件，用于在测试序列中存储所选择的里程碑处的通过/失败状态位。 在测试过程的选定点，元件可以被编程以指示设备已经通过与该过程中的所选点相关联的测试。 在对设备执行进一步测试之前，读取该元素以验证其在测试过程中通过先前的测试。 如果没有编写适当的元素，则设备被拒绝。 可以根据先前的测试步骤重新测试被拒绝的设备。 激光熔丝，电可编程熔丝或反熔丝用于存储测试结果。 使用电可写非易失性存储器元件允许在器件被封装之后对元件进行编程。