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    Delay locked loop circuit and method for testing the operability of the circuit
    2.
    发明授权
    Delay locked loop circuit and method for testing the operability of the circuit 有权
    延迟锁定环路电路和测试电路可操作性的方法

    公开(公告)号：US07075285B2

    公开(公告)日：2006-07-11

    申请号：US10844068

    申请日：2004-05-12

    申请人： Richard Chin

    发明人： Richard Chin

    IPC分类号： G01R23/175 ,  G01R31/08

    CPC分类号： H03L7/0814

    摘要： A delay locked loop (DLL) circuit and method for testing the operability of the circuit utilizes one or more test signal sources and a test signal receiver to selectively transmit test signals, for example, static test signals, through an array of delay elements of the DLL circuit. The resulting output signals of the array are used to determine whether any delay element or a tap selector of the DLL circuit has malfunctioned, e.g., stuck-at fault.

    摘要翻译： 用于测试电路的可操作性的延迟锁定环路（DLL）电路和方法利用一个或多个测试信号源和测试信号接收器来选择性地传输测试信号，例如静态测试信号，通过一系列延迟元件 DLL电路。 阵列的结果输出信号用于确定DLL电路的任何延迟元件或分接选择器是否发生故障，例如卡在故障状态。

    System and method for selectively affecting data flow to or from a memory device
    3.
    发明申请
    System and method for selectively affecting data flow to or from a memory device 审中-公开
    用于选择性地影响到或来自存储设备的数据流的系统和方法

    公开(公告)号：US20050033875A1

    公开(公告)日：2005-02-10

    申请号：US10878893

    申请日：2004-06-28

    申请人： Frank Cheung ,  Richard Chin

    发明人： Frank Cheung ,  Richard Chin

    IPC分类号： G06F3/00 ,  G06F5/06 ,  G06F12/00 ,  G06F13/16

    CPC分类号： G06F13/1605 ,  G06F13/1673

    摘要： A system for selectively affecting data flow to and/or from a memory device. The system includes a first mechanism for intercepting data bound for the memory device or originating from the memory device. A second mechanism compares a data level associated with the first mechanism to one or more thresholds and provides a signal in response thereto. A third mechanism selectively releases data from the first mechanism or from the memory device in response to the signal. In the specific embodiment, the first mechanism includes one or more First-In-First-Out (FIFO) memory buffers having level indicators that provide data level information. The third mechanism includes a memory manager that provides the signal to the one or more FIFO buffers or to the memory device based on the data level information, thereby causing the one or more FIFO buffers to release the data or accept data from the memory device.

    摘要翻译： 用于选择性地影响到和/或从存储器件的数据流的系统。 该系统包括用于截取为存储器件绑定或源自存储器件的数据的第一机制。 第二机制将与第一机制相关联的数据级别与一个或多个阈值进行比较，并提供响应于此的信号。 第三机构响应于该信号而选择性地从第一机构或从存储器件释放数据。 在具体实施例中，第一机制包括具有提供数据级别信息的级别指示符的一个或多个先进先出（FIFO）存储器缓冲器。 第三机制包括基于数据级信息向一个或多个FIFO缓冲器或存储器件提供信号的存储器管理器，从而使一个或多个FIFO缓冲器释放数据或从存储器件接收数据。

    Method for adaptive test generation via feedback from dynamic emulation
    4.
    发明授权
    Method for adaptive test generation via feedback from dynamic emulation 失效
    通过动态仿真反馈生成自适应测试的方法

    公开(公告)号：US06484135B1

    公开(公告)日：2002-11-19

    申请号：US09386012

    申请日：1999-08-30

    申请人： Richard Chin ,  Deb Aditya Mukherjee

    发明人： Richard Chin ,  Deb Aditya Mukherjee

    IPC分类号： G06F9455

    CPC分类号： G06F17/5022

    摘要： A function for adaptively generating test vectors to verify the behavior of a digital system. The function utilizes one or more user-defined verification directives for directing the generation of the test vectors to areas of interest within the digital system. An emulator of the digital system provides dynamic feedback of internal state information to the test vector generation function during the verification. The test vector generation function adaptively generates future verification test vectors based on the user-defined verification directives in view of the internal state information feedback received from the emulator.

    摘要翻译： 用于自适应地生成测试向量以验证数字系统的行为的功能。 该功能利用一个或多个用户定义的验证指令来将测试向量的生成引导到数字系统内的感兴趣区域。 数字系统的仿真器在验证期间向内部状态信息提供动态反馈给测试向量生成功能。 鉴于从仿真器接收的内部状态信息反馈，测试向量生成功能根据用户定义的验证指令自适应地生成未来的验证测试向量。

    Digital video thermal electric controller loop utilizing video reference pixels on focal plane arrays
    7.
    发明申请
    Digital video thermal electric controller loop utilizing video reference pixels on focal plane arrays 审中-公开
    数字视频热电控制器回路利用焦平面阵列上的视频参考像素

    公开(公告)号：US20050023469A1

    公开(公告)日：2005-02-03

    申请号：US10629042

    申请日：2003-07-28

    申请人： Richard Chin ,  Frank Cheung ,  Eric Sutton

    发明人： Richard Chin ,  Frank Cheung ,  Eric Sutton

    IPC分类号： G01J1/10 ,  G01J5/02 ,  G01J5/06

    CPC分类号： G01J5/061 ,  H04N5/361 ,  H04N5/3651

    摘要： A system and method for stabilizing the temperature of a detector array. The novel invention (100) includes one or more video reference pixels (52) adapted to output a reference signal that is responsive to the temperature of the detector array (50), and a mechanism for adjusting the temperature of the detector array (50) based on the reference signal. In the illustrative embodiment, the mechanism includes a thermal electric cooler (112) and a processor (104) running a control algorithm (106) which calculates the amount of current which should be applied to the thermal electric cooler (112) based on the reference signal from the video reference pixels (52). The video reference pixels (52) are constructed from the same substrate as the detector array (50), but are constructed in a manner such that they do not respond to changes in scene illumination.

    摘要翻译： 用于稳定检测器阵列的温度的系统和方法。 新颖的发明（100）包括适于输出响应于检测器阵列（50）的温度的参考信号的一个或多个视频参考像素（52），以及用于调节检测器阵列（50）的温度的机构， 基于参考信号。 在说明性实施例中，该机构包括运行控制算法（106）的热电冷却器（112）和处理器（104），该控制算法（106）基于参考来计算应施加到热电冷却器（112）的电流量 来自视频参考像素（52）的信号。 视频参考像素（52）由与检测器阵列（50）相同的衬底构成，但是以使得它们不对场景照明中的变化做出响应的方式构造。

    Thermal imaging device
    8.
    发明授权
    Thermal imaging device 失效
    热成像装置

    公开(公告)号：US5682035A

    公开(公告)日：1997-10-28

    申请号：US524200

    申请日：1995-09-06

    申请人： Tim Gallagher ,  Richard Chin

    发明人： Tim Gallagher ,  Richard Chin

    IPC分类号： G03B41/00 ,  H04N5/243 ,  H04N5/33 ,  H04N5/57

    CPC分类号： H04N5/3651 ,  H04N5/33

    摘要： A thermal infrared imaging device (10) includes a thermal detector (50) having a linearly-arrayed plurality of spaced apart detector elements (50', 50", 50"', . . . ). A scene to be viewed is scanned across the detector (50) with successive fields of the scene shifted according the spacing between adjacent detector elements (50', 50", 50"', . . . ) in order to capture image information for the entire scene by interlacing of successive scan lines from the plurality of detector elements (50', 50", 50"', . . . ). Each complete scan of the viewed scene across the detector (50) creates an image field including a scan line for each detector element (50', 50", 50"', . . . ). Each scan line includes plural pixels, or picture elements of the viewed scene, each having a value indicative of the thermal infrared brightness of the viewed scene at the corresponding location along the scan line. An scan-line sum for each scan line is created by adding the absolute values of the pixel values for each scan line. The average of these scan-line sums is employed as a gain control factor to control the brightness of a visible image replicating the viewed scene. Further, the value of a median of the scan-line sums is used to limit gain variations which would otherwise be effected were the line-sum averages alone used to control the gain factor. Accordingly, even when a localized highly-radiant heat source (such as a fire) is within the field of view of the thermal imaging device, then in areas of the image away from the brightness caused by the fire the image does not go dark and a visible image good contrast is still maintained allowing features of the image to be viewed.

    摘要翻译： 热红外成像装置（10）包括具有线性排列的多个间隔开的检测器元件（50'，50“，50”“...）的热检测器（50）。 要查看的场景扫描在检测器（50）上，其中场景的连续场根据相邻检测器元件（50'，50“，”“”“之间的间距）移位，以便捕获图像信息 对于整个场景，通过从多个检测器元件（50'，50“，50”“...）中连续扫描线的交错。 扫描器（50）上的所观看场景的每次完整扫描产生包括每个检测器元件（50'，50“，50”“...）的扫描线的图像场。 每个扫描线包括多个像素或所观看场景的图像元素，每个像素具有指示沿着扫描线的相应位置处的所观看场景的热红外亮度的值。 每个扫描线的扫描线总和通过添加每个扫描线的像素值的绝对值来创建。 这些扫描线和的平均值被用作增益控制因子来控制复制观看场景的可视图像的亮度。 此外，扫描线和的中值的值用于限制增益变化，否则将仅仅用于控制增益因子的线总和平均值来实现。 因此，即使当局部高度辐射热源（如火灾）在热成像装置的视野内时，在图像远离由火焰引起的亮度的区域中，图像也不会变暗， 仍然保持可见图像良好的对比度，允许观看图像的特征。

    Document Collaboration System and Method
    9.
    发明申请
    Document Collaboration System and Method 审中-公开
    文件协作系统与方法

    公开(公告)号：US20080059539A1

    公开(公告)日：2008-03-06

    申请号：US11836087

    申请日：2007-08-08

    申请人： Richard Chin ,  Jason Lee

    发明人： Richard Chin ,  Jason Lee

    IPC分类号： G06F17/30

    CPC分类号： G06Q10/10

    摘要： A system that allows users to create, edit, manage, collaborate and communicate on documents such as word processor documents, spreadsheets, databases, slides, and diagram editors is disclosed. Each document type is broken down into basic workable elements. Each change to a document is tracked in a centralized database under control of a database management system, and users use a web browser and/or desktop as the client front end. Changes to the document are communicated back and forth to the database via a rich asynchronous javascript and XML web page. Changes from multiple sources or sessions can be compared with each other in a side-by-side display environment.

    摘要翻译： 公开了允许用户在诸如文字处理器文档，电子表格，数据库，幻灯片和图表编辑器之类的文档上创建，编辑，管理，协作和通信的系统。 每个文档类型都分为基本的可操作元素。 在数据库管理系统的控制下，在一个集中式数据库中跟踪对文档的每次更改，用户使用Web浏览器和/或桌面作为客户机前端。 文档的更改通过丰富的异步JavaScript和XML网页来回传递到数据库。 来自多个来源或会话的更改可以在并排显示环境中相互比较。

    Self-aligning data path converter for multiple clock systems
    10.
    发明授权
    Self-aligning data path converter for multiple clock systems 有权
    用于多个时钟系统的自对准数据路径转换器

    公开(公告)号：US07275174B2

    公开(公告)日：2007-09-25

    申请号：US11507677

    申请日：2006-08-22

    申请人： Frank Nam Go Cheung ,  Richard Chin

    发明人： Frank Nam Go Cheung ,  Richard Chin

    IPC分类号： G06F1/04 ,  G06F1/12

    CPC分类号： H03L7/00 ,  H03K5/135 ,  H04L7/0008 ,  H04L7/0045 ,  H04L7/0079 ,  H04L7/02

    摘要： A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.

    摘要翻译： 一种用于将与第一时钟信号（22）同步的输入信号（24）与第二时钟信号（26）对准的系统和方法。本发明包括一种用于产生第三时钟信号（354）和一个装置 352），用于根据第三时钟信号（354）加载输入信号（24），并根据第二时钟信号（26）读出输出信号。 在说明性实施例中，本发明用于传感器系统（350）中，以将与数据捕获时钟（22）同步的检测器输入数据（24）与信号处理时钟（26）对准。 寄存器（352）用作在采样的实际时间和处理系统（102）在采样数据中时钟之间的数据路径转换级。