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13 条记录 (耗时 0.017 秒)

    Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells
    5.
    发明授权
    Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells 失效
    用于制造组件以限制编程电压并且使用EEPROM存储器单元稳定结合在电气设备中的电压的工艺

    公开(公告)号：US5322803A

    公开(公告)日：1994-06-21

    申请号：US946797

    申请日：1992-09-18

    申请人： Paolo Cappelletti ,  Giuseppe Corda ,  Paolo Ghezzi ,  Carlo Riva ,  Bruno Vajana

    发明人： Paolo Cappelletti ,  Giuseppe Corda ,  Paolo Ghezzi ,  Carlo Riva ,  Bruno Vajana

    IPC分类号： G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L21/266

    CPC分类号： H01L29/66106 ,  H01L27/115 ,  H01L27/11517 ,  Y10S148/174 ,  Y10S438/983

    摘要： The manufacturing process comprises a first step of formation of an N type sink on a single-crystal silicon substrate, a second step of formation of an active area on the surface of said sink, a third step of implantation of N- dopant in a surface region of the sink inside said active area, a fourth step of growth of a layer of gate oxide over said region with N- dopant, a fifth step of N+ implantation inside said N- region, a sixth step of P+ implantation in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

    摘要翻译： 该制造方法包括在单晶硅衬底上形成N型吸收体的第一步骤，在所述吸收体的表面上形成有源区的第二步骤，在表面上注入N掺杂剂的第三步骤 在所述有源区域内的宿的区域，在所述区域上用N-掺杂剂生长栅极氧化物层的第四步骤，在所述N-区域内N +注入的第五步骤，P +植入在横向位移中的第六步骤 相对于所述N +区域的位置，以及形成所述N +和P +区域的外部触点的第七步骤。 因此，获得了具有截止电压的齐纳二极管限幅器，该截止电压随着时间而稳定，并且不依赖于温度，并且不需要相对于完成EEPROM存储器单元通常所需的那些处理步骤。

    High voltage capacitor
    7.
    发明授权
    High voltage capacitor 失效
    高压电容器

    公开(公告)号：US06188121B1

    公开(公告)日：2001-02-13

    申请号：US09119115

    申请日：1998-07-20

    申请人： Livio Baldi ,  Paolo Ghezzi ,  Alfonso Maurelli

    发明人： Livio Baldi ,  Paolo Ghezzi ,  Alfonso Maurelli

    IPC分类号： H01L2900

    CPC分类号： H01L28/60 ,  H01L27/0805 ,  H01L29/94

    摘要： A high voltage capacitor, integratable monolithically on a semiconductor substrate which accommodates a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer, comprises two elementary capacitors having a first common conductive plate which is formed in the first layer of polycrystalline silicon. Each of these elementary capacitors has a second conductive plate formed in the second layer of polycrystalline silicon above the first plate, and includes said interpoly dielectric layer as an isolation dielectric between the two plates.

    摘要翻译： 一个高电压电容器，整体地集成在半导体衬底上，该半导体衬底上容纳由第二层多晶硅隔绝的第一多晶硅层覆盖的场氧化物区域，该第二层由多晶硅电介质层隔开，包括两个基本电容器，其具有第一公共导电板， 形成在第一层多晶硅中。 这些基本电容器中的每一个具有形成在第一板上方的第二多晶硅层中的第二导电板，并且包括作为两个板之间的隔离电介质的所述互聚电介质层。

    Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process
    8.
    发明授权
    Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process 有权
    通过自对准源工艺制造的存储器单元的矩阵，包括ROM存储器单元和相关的制造工艺

    公开(公告)号：US06812531B1

    公开(公告)日：2004-11-02

    申请号：US09303055

    申请日：1999-04-30

    申请人： Livio Baldi ,  Paolo Ghezzi

    发明人： Livio Baldi ,  Paolo Ghezzi

    IPC分类号： H01L2976

    CPC分类号： H01L27/11246 ,  H01L27/112

    摘要： Matrix of memory cells formed using a method allowing for a self-alignment of the respective source region with the respective field oxide layer and the respective overlying polysilicon layer of each single cell of the matrix, the matrix including at least one first ROM memory cell suitable for permanently storing a first logic level, associated with a respective row and a respective column of the matrix, the first cell including a silicon substrate of a first conductivity type over which a first isolation region and a second isolation region are formed delimiting therebetween a longitudinal stripe, a gate element extending transversally through the stripe from at least one side of the first isolation region to at least one side of the second isolation region, a third region of a second conductivity type and a fourth region of a second conductivity type formed in the substrate along the stripe, and a field oxide region adapted to prevent the formation of a conductive channel in the substrate, and at least a second ROM cell for permanently storing a second logic level, identical to the first ROM memory cell but not provided with the field oxide region.

    摘要翻译： 使用允许各个源区域与相应的场氧化物层和矩阵的每个单个单元的相应的上覆多晶硅层的自对准的方法形成的存储器单元的矩阵，该矩阵包括至少一个第一ROM存储器单元 用于永久存储与矩阵的相应行和相应列相关联的第一逻辑电平，第一单元包括第一导电类型的硅衬底，在其上形成第一隔离区域和第二隔离区域，第一隔离区域和第二隔离区域之间界定纵向 条形，从第一隔离区的至少一侧横穿条带延伸至第二隔离区的至少一侧的栅极元件，形成第二导电类型的第三区域和第二导电类型的第四区域 沿着条带的衬底，以及适于防止在子层中形成导电沟道的场氧化物区域 并且至少第二ROM单元用于永久地存储第二逻辑电平，与第一ROM存储器单元相同但不具有场氧化物区域。

    Electrically erasable and programmable non-volatile memory cell
    10.
    发明授权
    Electrically erasable and programmable non-volatile memory cell 有权
    电可擦除和可编程的非易失性存储单元

    公开(公告)号：US06876033B2

    公开(公告)日：2005-04-05

    申请号：US10606164

    申请日：2003-06-25

    申请人： Paolo Cappelletti ,  Paolo Ghezzi ,  Alfonso Maurelli ,  Loris Vendrame ,  Paola Zabberoni

    发明人： Paolo Cappelletti ,  Paolo Ghezzi ,  Alfonso Maurelli ,  Loris Vendrame ,  Paola Zabberoni

    IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L29/788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

    摘要： An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

    摘要翻译： 提供电可擦除和可编程的存储单元。 存储单元包括浮置栅极MOS晶体管和用于将电荷注入浮置栅极的双极晶体管。 浮置栅极晶体管具有形成在第一阱中的源极区和漏极区，沟道限定在漏极和源极区之间，控制栅极区以及在沟道和控制栅极区上延伸的浮动栅极。 双极晶体管具有形成在第一阱中的发射极区域，由第一阱构成的基极区域和由沟道组成的集电极区域。 存储单元包括与第一阱绝缘的第二阱，并且控制栅区形成在第二阱中。 本发明的另外的实施例提供了包括至少一个这样的存储单元的存储器，包括这种存储器的电子设备，以及集成存储器单元和擦除存储器单元的方法。