公开(公告)号：US07827386B2

公开(公告)日：2010-11-02

申请号：US10611377

申请日：2003-06-30

申请人： Louis A. Lippincott ,  Chin Hong Cheah

发明人： Louis A. Lippincott ,  Chin Hong Cheah

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F9/4494

摘要： A first set of instructions and incoming data are provided to a first processing unit of a data driven processor, to operate upon the incoming data. The first processing unit, in response to recognizing that the first set of instructions will require either reading from or writing to external memory, sets up a logical channel between a second processing unit of the processor and the external memory, to transfer additional data between the external memory and the second processing unit. This capability may be implemented by the addition of a control port, separate from data ports, to the first processing unit, where the control port allows the first processing unit to write addressing information and mode information (including the location of the additional data) for reading or writing the additional data via a memory access unit data channel of the processor.

摘要翻译： 将第一组指令和输入数据提供给数据驱动处理器的第一处理单元，以对输入的数据进行操作。 第一处理单元响应于识别第一组指令需要从外部存储器读取或写入外部存储器，在处理器的第二处理单元和外部存储器之间建立逻辑通道，以在第二处理单元之间传送附加数据 外部存储器和第二处理单元。 该能力可以通过添加与数据端口分离的控制端口到第一处理单元来实现，其中控制端口允许第一处理单元将寻址信息和模式信息（包括附加数据的位置）写入 通过处理器的存储器访问单元数据通道读取或写入附加数据。

公开(公告)号：US07020891B1

公开(公告)日：2006-03-28

申请号：US09672372

申请日：2000-09-28

申请人： Louis A. Lippincott

发明人： Louis A. Lippincott

IPC分类号： H04N7/173

CPC分类号： H04N7/17318 ,  H04N21/2347 ,  H04N21/26606 ,  H04N21/26613 ,  H04N21/4405 ,  H04N21/4623 ,  H04N21/4661 ,  H04N21/4667 ,  H04N21/47202 ,  H04N21/6587 ,  H04N21/835

摘要： A device is provided that includes a first processor connected to a communications channel device. The communications device is capable of receiving and transmitting information to a video-on-demand (VOD) service provider. A VOD content decoder is provided that is conencted to the first processor. A video and audio formatting processor is provided that is connected to the first processor and the content decoder. An index memory is provided that is connected to the first processor. The index memory stores a plurality of VOD program segment representations of either whole VOD program content or partial VOD program content. Also provided is a method that includes selecting a start and stop time for recording a representation of a segment of at least one VOD program. The method also includes converting a VOD program identifier of at least one VOD program to a text representation. Also, either converting the text representation of the VOD program identifier of at least one VOD program into a unique encoded digital representation or receiving a unique encoded digital representation from the VOD service provider. Converting the start and stop time for a segment of at least one VOD program to a digital representation. And storing the VOD program identifier encoded digital representation and the start and stop digital representation in an index memory.

摘要翻译： 提供了一种包括连接到通信信道设备的第一处理器的设备。 通信设备能够接收和发送信息到视频点播（VOD）服务提供商。 提供一种与第一处理器相连的VOD内容解码器。 提供了连接到第一处理器和内容解码器的视频和音频格式化处理器。 提供了连接到第一处理器的索引存储器。 索引存储器存储整个VOD节目内容或部分VOD节目内容的多个VOD节目片段表示。 还提供了一种方法，其包括选择用于记录至少一个VOD节目的片段的表示的开始和停止时间。 该方法还包括将至少一个VOD节目的VOD节目标识符转换为文本表示。 此外，将至少一个VOD节目的VOD节目标识符的文本表示转换为唯一的编码数字表示，或者从VOD服务提供商接收唯一的编码数字表示。 将至少一个VOD程序的段的开始和停止时间转换为数字表示。 并将VOD节目标识符编码的数字表示和起始和停止数字表示存储在索引存储器中。

公开(公告)号：US06366516B1

公开(公告)日：2002-04-02

申请号：US09753005

申请日：2000-12-29

申请人： Louis A. Lippincott

发明人： Louis A. Lippincott

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A memory subsystem that includes a dynamic random-access memory (DRAM) having cells organized as an array of rows and columns, the cells being individually accessed by specifying a row address and a column address. An additional cell that stores a charge level is associated with each row of the DRAM. The charge level is characteristic of the charge level of the associated DRAM row, and is refreshed by a secondary or primary refresh cycle to the associated DRAM row. A threshold detector outputs a refresh signal when the charge of the additional cell drops below a predetermined threshold. Circuitry responsive to the refresh signal collects the row address of the additional cell and sends it to logic that generates a primary refresh cycle to the associated row address of the DRAM.

摘要翻译： 一种包括动态随机存取存储器（DRAM）的存储器子系统，其具有被组织成行和列的阵列的单元，通过指定行地址和列地址来单独访问单元。 存储电荷电平的附加单元与DRAM的每一行相关联。 充电电平是相关DRAM行的充电电平的特征，并且被辅助或主刷新周期刷新到相关的DRAM行。 当附加单元的电荷下降到预定阈值以下时，阈值检测器输出刷新信号。 响应于刷新信号的电路收集附加单元的行地址，并将其发送到生成主要刷新周期的逻辑到DRAM的相关行地址。

公开(公告)号：US5649142A

公开(公告)日：1997-07-15

申请号：US476061

申请日：1995-06-07

申请人： Gary Lavelle ,  Louis A. Lippincott ,  Kevin Harney ,  Dinesh G. Rao

发明人： Gary Lavelle ,  Louis A. Lippincott ,  Kevin Harney ,  Dinesh G. Rao

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/10 ,  G06F13/00

CPC分类号： G06F12/1081 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/3816 ,  G06F9/3863 ,  G06F9/3885 ,  G06F9/3887

摘要： A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as system address space, and for accessing a service routine in response to a page fault, are described. In one embodiment, the apparatus for translating comprises a processor; a page table having a translation mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive values in the comparison value register until a match comparison value is found. If a match comparison value is found, a programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress to provide the second address. If a match comparison value is not found, a fault interrupt is generated to interrupt the translation and the processor accesses a service routine in accordance with the fault interrupt.

摘要翻译： 一种用于将诸如处理器地址空间的第一地址空间中的第一地址转换到诸如系统地址空间的第二地址空间中的第二地址并且响应于页错误而访问服务例程的方法和装置 ，被描述。 在一个实施例中，用于翻译的装置包括处理器; 具有翻译屏蔽寄存器，比较值寄存器和替换值寄存器的页表; 以及耦合到比较值寄存器和替换值寄存器的比较器。 使用翻译掩码寄存器内的可编程掩码来分割虚拟地址。 第一子地址包括第一地址的比特的子集，第二子地址包括第一地址的剩余比特。 第一个子地址在转换掩码寄存器中用可编程掩码值进行掩码，并通过比较器与比较值寄存器中的连续值进行比较，直到找到匹配比较值。 如果找到匹配比较值，则与匹配比较值相对应的替换值寄存器中的可编程替换值与第二子地址相连接以提供第二地址。 如果未找到匹配比较值，则产生故障中断以中断转换，并且处理器根据故障中断访问服务程序。

公开(公告)号：US5345554A

公开(公告)日：1994-09-06

申请号：US901434

申请日：1992-06-19

申请人： Louis A. Lippincott ,  Serge Rutman

发明人： Louis A. Lippincott ,  Serge Rutman

IPC分类号： H04N5/262 ,  G06F3/153 ,  G09G5/02 ,  G09G5/36 ,  G09G5/39 ,  G09G5/397 ,  G09G5/399 ,  H04N5/445 ,  H04N9/75 ,  G06F15/20

CPC分类号： G09G5/397 ,  H04N5/44504 ,  G09G2340/125 ,  G09G5/363

摘要： An apparatus for processing visual data includes a first video random access memory (VRAM) for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first VRAM by a data bus and a storage bus. The apparatus is capable of receiving at least a second VRAM for storing at least a second bit plane of visual data in at least a second format different from the first format. The received VRAMs are coupled to the graphics controller by data and storage busses. The visual data stored on the VRAMs are merged into a pixel stream which is then converted to analog form by a digital to analog converter. Data transfer addresses are generated for each of the VRAMs simultaneously, sequentially or in overlapping timed relationship.

摘要翻译： 一种用于处理视觉数据的装置包括用于以第一格式存储视觉数据的第一位平面的第一视频随机存取存储器（VRAM）。 图形控制器通过数据总线和存储总线耦合到第一VRAM。 该装置能够接收至少一个第二VRAM，用于至少存储与第一格式不同的至少第二格式的视觉数据的至少第二位平面。 所接收的VRAM通过数据和存储总线耦合到图形控制器。 存储在VRAM上的视觉数据被合并成像素流，然后通过数模转换器将其转换成模拟形式。 同时，依次或以重叠的定时关系为每个VRAM生成数据传输地址。

公开(公告)号：US5339442A

公开(公告)日：1994-08-16

申请号：US954743

申请日：1992-09-30

申请人： Louis A. Lippincott

发明人： Louis A. Lippincott

IPC分类号： G06F13/18 ,  G06F13/362 ,  G06F13/364

CPC分类号： G06F13/362 ,  G06F13/18

摘要： A request arbitration device is provided for prioritizing requests in a data processing system. A series of requests may arrive at the arbitration device at differing arrival times. The requests are accumulated to form a set of requests which is applied to a priority decode without any information on their relative arrival times. The priority device applies a fixed predetermined priority scheme to these requests. Simultaneously with the prioritizing of the first set of requests by the priority decode, a second set of requests may arrive at different arrival times. The requests of this second set of requests are likewise accumulated by the arbitration logic of a present invention. When arbitration of the first set of requests is complete, the second set of requests is then applied to the priority decode, again without any information with respect to their relative arrival times. The second set of requests is prioritized according to the same fixed predetermined priority scheme as the first set.

摘要翻译： 提供请求仲裁装置用于在数据处理系统中优先处理请求。 一系列请求可能在不同到达时间到达仲裁设备。 这些请求被积累以形成一组请求，该请求被应用于优先解码，而没有关于其相对到达时间的任何信息。 优先级设备对这些请求应用固定的预定优先级方案。 与通过优先解码对第一组请求进行优先排列同时，第二组请求可以到达不同的到达时间。 第二组请求的请求同样地由本发明的仲裁逻辑积累。 当第一组请求的仲裁完成时，第二组请求然后再次应用于优先级解码，而没有关于它们的相对到达时间的任何信息。 第二组请求根据与第一组相同的固定预定优先级方案进行优先排序。

公开(公告)号：US5335321A

公开(公告)日：1994-08-02

申请号：US901383

申请日：1992-06-19

申请人： Kevin Harney ,  Louis A. Lippincott

发明人： Kevin Harney ,  Louis A. Lippincott

IPC分类号： G06F3/14 ,  G06F13/42 ,  G06T11/00 ,  G09G5/36 ,  G06F15/20

CPC分类号： G09G5/363 ,  G06F13/423 ,  G06F3/14

摘要： The scalable platform architecture of the present video processing system invention includes a bus for transmitting data between various video processing subsystems. A graphics processing subsystem is coupled to the bus. A central processing unit is coupled to the bus and performs video processing. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The bus is provided with expansion connectors for detachably coupling to a video processing subsystem and a video capture system. The addition of the video processing subsystem and/or video capture subsystem accelerates the processing of the video processing system by performing video processing that would otherwise be performed by the central processing unit.

摘要翻译： 本发明的视频处理系统发明的可扩展平台架构包括用于在各种视频处理子系统之间传输数据的总线。 图形处理子系统耦合到总线。 中央处理单元耦合到总线并执行视频处理。 图形处理子系统适于接收视频存储器并且在接收到视频存储器时执行视频处理。 总线上设置有用于可拆卸地耦合到视频处理子系统和视频捕获系统的扩展连接器。 视频处理子系统和/或视频捕获子系统的添加通过执行由中央处理单元执行的视频处理来加速视频处理系统的处理。

公开(公告)号：US4620707A

公开(公告)日：1986-11-04

申请号：US508111

申请日：1983-06-27

申请人： Louis A. Lippincott

发明人： Louis A. Lippincott

IPC分类号： G11C5/00 ,  A63F9/22

CPC分类号： G11C5/00

摘要： The reprogrammable RAM cartridge of the present invention is adapted for use as a reprogrammable video game. The cartridge uses an optoisolator connected in a circuit between the shield and ground lines to detect the presence of a signal indicating that the cartridge is in a programmer, rather than in a video game unit. While in the programmer, the program stored in the RAM can be changed. However, when removed from the programmer, the cartridge acts like a standard video game cartridge.

摘要翻译： 本发明的可再编程RAM盒适用于可再编程视频游戏。 盒式光盘使用连接在屏蔽和接地线之间的电路中的光隔离器来检测指示盒位在编程器中而不是在视频游戏单元中的信号。 而在程序员中，存储在RAM中的程序可以改变。 但是，当从编程器中取出时，墨盒就像一个标准的视频游戏盒。

公开(公告)号：US08705632B2

公开(公告)日：2014-04-22

申请号：US11093732

申请日：2005-03-30

申请人： Eric F. Vannerson ,  Kalpesh D. Mehta ,  Louis A. Lippincott

发明人： Eric F. Vannerson ,  Kalpesh D. Mehta ,  Louis A. Lippincott

IPC分类号： H04N7/12

CPC分类号： H04N19/625 ,  H04N19/12 ,  H04N19/42 ,  H04N19/44 ,  H04N19/70 ,  H04N19/91

摘要： An apparatus includes a decoder to receive a compressed bit stream that is based on a coding standard. The decoder includes a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard. The decoder also includes a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.

摘要翻译： 一种装置包括：解码器，用于接收基于编码标准的压缩比特流。 解码器包括硬件加速器，用于对基于包括编码标准的多个编码标准中通用的操作的压缩比特流的一部分进行解码。 解码器还包括可编程元件，用于对基于编码标准特有的操作的压缩比特流的一部分进行解码。

公开(公告)号：US08063907B2

公开(公告)日：2011-11-22

申请号：US12548322

申请日：2009-08-26

申请人： Louis A. Lippincott ,  Patrick F. Johnson

发明人： Louis A. Lippincott ,  Patrick F. Johnson

IPC分类号： G06F15/16 ,  G06F15/80 ,  G06T1/00 ,  G09G5/36

CPC分类号： G06F15/8007 ,  G06F9/3879 ,  G06F9/5011 ,  G06F2209/507

摘要： A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the selection unit and the plurality of processing elements. In one embodiment, the register includes a plurality of general purpose registers (GPR), which are accessible by the plurality of processing elements, as well as the plurality of hardware accelerators. In one embodiment, at least one of the GPRs includes a bit to enable a processing element to enable access a selected hardware accelerator via the selection unit.

摘要翻译： 描述了在数据驱动架构中采用可选硬件加速器的方法和装置。 在一个实施例中，该装置包括多个处理元件（PE）。 多个硬件加速器耦合到选择单元。 寄存器耦合到选择单元和多个处理元件。 在一个实施例中，寄存器包括可由多个处理元件访问的多个通用寄存器（GPR）以及多个硬件加速器。 在一个实施例中，GPR中的至少一个包括位，以使处理元件能够经由选择单元访问所选择的硬件加速器。