公开(公告)号：US06751151B2

公开(公告)日：2004-06-15

申请号：US09827073

申请日：2001-04-05

申请人： Louis L. Hsu ,  Toshiaki K. Kirihata ,  Li-Kong Wang ,  Robert C. Wong

发明人： Louis L. Hsu ,  Toshiaki K. Kirihata ,  Li-Kong Wang ,  Robert C. Wong

IPC分类号： G11C800

CPC分类号： G06F12/0853 ,  G11C8/16 ,  H01L27/1104

摘要： An ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache having a cache speed in approximately the GHz range. This is accomplished by (1) a specially designed dual-port SRAM whose size is slightly larger than that of a conventional single port SRAM, and (2) the use of a dual dual-port SRAM architecture which doubles its speed by interleaved read and write operations. A first embodiment provides a 6-T (transistor) all nMOS dual-port SRAM cell. A second embodiment provides a dual port 7T-SRAM cell which has only one port for write, and both ports for read.

摘要翻译： 具有大约GHz范围内的高速缓存的超高速DDP-SRAM（双重双端口静态随机存取存储器）缓存。 这通过（1）专门设计的双端口SRAM（其尺寸略大于常规单端口SRAM）的实现来实现，以及（2）使用双重双端口SRAM架构，其通过交错读取将其速度加倍， 写操作。 第一实施例提供了6T（晶体管）全部nMOS双端口SRAM单元。 第二实施例提供了一个双端口7T-SRAM单元，其仅具有一个用于写入的端口，以及用于读取的两个端口。

公开(公告)号：US07283410B2

公开(公告)日：2007-10-16

申请号：US11308215

申请日：2006-03-13

申请人： Louis L. Hsu ,  Jack A. Mandelman ,  Robert C. Wong ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Jack A. Mandelman ,  Robert C. Wong ,  Chih-Chao Yang

IPC分类号： G11C7/00

CPC分类号： G11C11/4125

摘要： A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.

摘要翻译： 一种用于自动调整存储器件（例如SRAM阵列）中的一个或多个电参数的系统和方法。 该系统和方法实现SRAM感测子阵列，用于加速收集故障率数据，用于确定单个事件不起作息和主SRAM阵列性能之间的最佳权衡的操作点。 将加速失败率数据输入到在电离粒子环境中将初级SRAM存储器阵列的SEU灵敏度设定为预定故障率的算法。 为了提供符合最佳性能的SEU的免疫力，实时地维持预定的故障率。

公开(公告)号：US06654277B1

公开(公告)日：2003-11-25

申请号：US10143870

申请日：2002-05-14

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Robert C. Wong

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Robert C. Wong

IPC分类号： G11C1100

CPC分类号： G11C11/412

摘要： A static random access memory (SRAM) with cells in one portion having a higher beta ratio than the remaining cells of the array. In a first portion, cells have a low &bgr; ratio for high performance. A second portion of the array contains SRAM cells with a higher &bgr; ratio that are more stable than the cells in the first portion, but are somewhat slower.

摘要翻译： 静态随机存取存储器（SRAM），其中一部分中的单元具有比阵列的剩余单元更高的β比率。 在第一部分中，对于高性能，细胞具有低β比例。 该阵列的第二部分包含具有比第一部分中的细胞更稳定但具有较慢的β比率的SRAM细胞。

公开(公告)号：US08035126B2

公开(公告)日：2011-10-11

申请号：US11926399

申请日：2007-10-29

申请人： Phung T. Nguyen ,  Robert C. Wong

发明人： Phung T. Nguyen ,  Robert C. Wong

IPC分类号： H01L29/74

CPC分类号： H01L27/11 ,  G11C11/39 ,  H01L29/66659

摘要： A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.

摘要翻译： 公开了一种单晶体管静态随机存取存储器（1T SRAM）器件和电路实现方式。 1T SRAM器件包括在单元表面上的平面场效应晶体管（FET）和集成在FET一侧的垂直PNPN器件。 PNPN器件的PNP的基极与FET的发射极/集电极电气公共，并且PNPN器件的NPN的基极与FET的沟道区域电气公共。 PNPN器件的阳极引脚可以用作字线或位线。 还公开了一种形成1T SRAM器件的方法。

公开(公告)号：US07781797B2

公开(公告)日：2010-08-24

申请号：US11427406

申请日：2006-06-29

申请人： Phung T. Nguyen ,  Robert C. Wong

发明人： Phung T. Nguyen ,  Robert C. Wong

IPC分类号： H01L29/74

CPC分类号： H01L29/66659 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11

摘要： A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.

摘要翻译： 公开了一种单晶体管静态随机存取存储器（1T SRAM）器件和电路实现方式。 1T SRAM器件包括在单元表面上的平面场效应晶体管（FET）和集成在FET一侧的垂直PNPN器件。 PNPN器件的PNP的基极与FET的发射极/集电极电气公共，并且PNPN器件的NPN的基极与FET的沟道区域电气公共。 PNPN器件的阳极引脚可以用作字线或位线。 还公开了一种形成1T SRAM器件的方法。

公开(公告)号：US20090108356A1

公开(公告)日：2009-04-30

申请号：US11924053

申请日：2007-10-25

申请人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

发明人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

摘要翻译： 在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。 在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整 氧化层。 还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。 在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

公开(公告)号：US20090026523A1

公开(公告)日：2009-01-29

申请号：US11782079

申请日：2007-07-24

申请人： Robert C. Wong ,  Haining S. Yang

发明人： Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1211 ,  H01L29/785

摘要： A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.

摘要翻译： 在至少一个半导体鳍片的侧壁上形成栅极电介质和栅极导体层。 图案化栅极导体层，使得栅极电极形成在半导体鳍片的一部分的第一侧壁上，而在第一侧壁的相对侧上的第二侧壁不受栅电极控制。 因此，形成了部分选通的finFET，即在第一侧壁上具有栅电极且在第二侧壁上没有栅电极的finFET。 传统的双栅极finFET可以在同一衬底上与本发明的部分选通的鳍状FET形成，以在诸如SRAM电路的同一电路中提供具有不同导通电流的多个finFET。

公开(公告)号：US07355906B2

公开(公告)日：2008-04-08

申请号：US11420049

申请日：2006-05-24

申请人： Rajiv V. Joshi ,  Yue Tan ,  Robert C. Wong

发明人： Rajiv V. Joshi ,  Yue Tan ,  Robert C. Wong

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

摘要： A novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions. Both methods improve stability by eliminating half-select mode and facilitate rail to rail data transfer in and out of the SRAM cell without disturbing the other cells.

摘要翻译： 一种新颖的半导体SRAM单元结构，其包括至少两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。 在一个实施例中，8T SRAM单元结构实现了用于实现具有增强的稳定性的列选择（CS）和行选择（WL）单元存储访问的串行门控特征。 特别地，8-T方法增加了两个传递门，两个串联的晶体管器件连接在两个交叉耦合的反相器的互补节点处，以控制列选择和行（字）选择。 在另一实施例中，9T SRAM单元结构包括具有增强的稳定性的实现列选择（CS）和行选择（WL）单元存储访问的传输门。 9-T方法增加了三个晶体管来执行ANDING功能，以分离行选择和列选择信号功能。 这两种方法通过消除半选择模式提高稳定性，并有助于轨至轨数据传输进出SRAM单元，而不会干扰其他单元。

公开(公告)号：US06876040B1

公开(公告)日：2005-04-05

申请号：US10735169

申请日：2003-12-12

申请人： Hsingjen Wann ,  Ying Zhang ,  Robert C. Wong ,  An Steegen

发明人： Hsingjen Wann ,  Ying Zhang ,  Robert C. Wong ,  An Steegen

IPC分类号： H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12 ,  H01L27/01 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0392

CPC分类号： H01L27/1207 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： A SRAM cell fabricated in SSOI (selective silicon on insulator) comprises cross coupled PFET pull-up devices P1, P2 and NFET pull-down devices N1, N2, with the P1, P2 devices being connected to the power supply and the N1, N2 devices being connected to the ground. A first passgate NL is coupled between a first bitline and the junction of the devices P1 and N1, with its gate coupled to a wordline, and a second passgate NR is coupled between a second bitline and the junction of devices P2 and N2, with its gate coupled to the wordline. Each of the pull-up devices P1, P2, the pull-down devices N1, N2, and the first and second passgates NL, NR are fabricated with selective SOI, with buried oxide being selectively provided under the drains of the pull-up devices P1 and P2, the drains of the pull-down devices N1 and N2, and the sources and drains of the passgate devices NL and NR.

摘要翻译： 在SSOI（选择性绝缘体硅）上制造的SRAM单元包括交叉耦合的PFET上拉器件P1，P2和NFET下拉器件N1，N2，其中P1，P2器件连接到电源，N1，N2 设备连接到地面。 第一通路门NL耦合在第一位线和器件P1和N1的接点之间，其栅极耦合到字线，并且第二通路门NR耦合在第二位线和器件P2和N2的接点之间，其中 门连接到字线。 上拉器件P1，P2，下拉器件N1，N2以及第一和第二通路NL，NR中的每一个被制造成具有选择性SOI，其中掩埋氧化物选择性地设置在上拉器件的漏极下 P1和P2，下拉装置N1和N2的下水道，以及通道装置NL和NR的源极和漏极。

公开(公告)号：US5681770A

公开(公告)日：1997-10-28

申请号：US645726

申请日：1996-05-14

申请人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

发明人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/972

摘要： A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.