公开(公告)号：US08536462B1

公开(公告)日：2013-09-17

申请号：US12692397

申请日：2010-01-22

申请人： Robert Francis Darveaux ,  Ludovico E. Bancod ,  Marnie Ann Mattei ,  Timothy Lee Olson

发明人： Robert Francis Darveaux ,  Ludovico E. Bancod ,  Marnie Ann Mattei ,  Timothy Lee Olson

IPC分类号： H05K1/16 ,  H05K1/00

CPC分类号： H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48265 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/181 ,  H05K3/363 ,  H05K2201/0379 ,  H05K2201/0979 ,  H05K2201/10356 ,  H05K2201/1053 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A flex circuit package includes a package body enclosing an electronic component and a first surface of the substrate. Columns are physically and electrically connected to first traces of the substrate, the columns extending through the package body. A flexible circuit connector has first terminals connected to the columns. The flexible circuit connector further includes second terminals that provide an electrical interconnection structure for electrical connection to a second electronic component structure. By connecting the flexible circuit connector to the columns extending through the package body, special routing of traces of the substrate of the flex circuit package to provide an interface for the flexible circuit connector is avoided.

摘要翻译： 柔性电路封装包括封装电子部件和基板的第一表面的封装体。 柱物理和电连接到衬底的第一迹线，柱延伸穿过封装主体。 柔性电路连接器具有连接到列的第一端子。 柔性电路连接器还包括提供用于与第二电子部件结构电连接的电互连结构的第二端子。 通过将柔性电路连接器连接到延伸穿过封装体的列，避免了柔性电路封装的基板的迹线的特殊布线，以提供用于柔性电路连接器的接口。

公开(公告)号：US20080169541A1

公开(公告)日：2008-07-17

申请号：US11250816

申请日：2005-10-14

申请人： Jeffrey Alan Miks ,  Robert Francis Darveaux ,  Chung-Hsing Tzu

发明人： Jeffrey Alan Miks ,  Robert Francis Darveaux ,  Chung-Hsing Tzu

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/3107 ,  H01L23/49541 ,  H01L24/48 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory card comprising a leadframe having a plurality of contacts. Electrically connected to the leadframe is at least one semiconductor die. A body at least partially encapsulates the leadframe and includes opposed top and bottom surfaces, an opposed pair of longitudinal sides, and an opposed pair of lateral sides. The contacts of the leadframe are exposed in the bottom surface of the body and extend to one of the lateral sides thereof.

摘要翻译： 一种存储卡，包括具有多个触点的引线框架。 电连接到引线框架是至少一个半导体管芯。 主体至少部分地封装引线框架并且包括相对的顶表面和底表面，相对的一对纵向侧面和相对的一对侧边。 引线框架的触点暴露在主体的底表面中并延伸到其一个侧面。

公开(公告)号：US08207022B1

公开(公告)日：2012-06-26

申请号：US12931326

申请日：2011-01-27

申请人： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

发明人： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

IPC分类号： B29C31/00 ,  H01L23/29

CPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105

摘要： An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

摘要翻译： 曝光的芯片包覆成型的倒装芯片封装包括衬底。 芯片安装在基板的上表面上。 该包装还包括填充模具的活性表面和基材的上表面之间的空间的模具盖。 模具帽包括主表面，从基板的上表面延伸到主表面的侧壁，与模具的非活性表面共面并从模具的非活性表面的外围边缘向外延伸的环形表面，并且突出 表面在主表面和环形表面之间延伸。 模具盖不覆盖模具的非活性表面，使得从模具到周围环境的热传递最大化并且封装厚度最小化。

公开(公告)号：US07932170B1

公开(公告)日：2011-04-26

申请号：US12144145

申请日：2008-06-23

申请人： Ronald Patrick Huemoeller ,  Roger D. St. Amand ,  Robert Francis Darveaux

发明人： Ronald Patrick Huemoeller ,  Roger D. St. Amand ,  Robert Francis Darveaux

IPC分类号： H01L21/44

CPC分类号： H01L21/4853 ,  H01L24/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14

摘要： A method includes forming a patterned buildup layer on a first surface of a dielectric layer, the patterned buildup layer including a patterned buildup layer opening exposing a trace coupled to the dielectric layer. A conductor layer is flash plated on the patterned buildup layer and within the patterned buildup layer opening. The patterned buildup layer opening is filled with a blanket conductive filler layer. The blanket conductive filler layer and the conductor layer are planarized to form a flip chip bump.

摘要翻译： 一种方法包括在电介质层的第一表面上形成图案化的聚集层，所述图案化的构建层包括图案化的积层层，其暴露耦合到电介质层的迹线。 导体层被闪镀在图案化的积层和图案化的积层层开口内。 图案化的积层层开口填充有覆盖层导电填料层。 将覆盖层导电填料层和导体层平坦化以形成倒装芯片凸块。

公开(公告)号：US08536458B1

公开(公告)日：2013-09-17

申请号：US12414220

申请日：2009-03-30

申请人： Robert Francis Darveaux ,  David McCann ,  John McCormick ,  Louis W. Nicholls

发明人： Robert Francis Darveaux ,  David McCann ,  John McCormick ,  Louis W. Nicholls

IPC分类号： H05K1/03 ,  H05K1/11

CPC分类号： H05K1/111 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/1146 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1412 ,  H01L2224/14133 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/15311 ,  H05K3/00 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： An electronic component package includes a substrate having an upper surface. Traces on the upper surface of the substrate extend in a longitudinal direction. The traces have a first latitudinal width in a latitudinal direction, the latitudinal direction being perpendicular to the longitudinal direction. Rectangular copper pillars are attached to bond pads of an electronic component, the copper pillars having a longitudinal length and a latitudinal second width. The latitudinal second width of the copper pillars is equal to and aligned with the first latitudinal width of the traces. Further, the longitudinal length of the copper pillars is parallel with the longitudinal direction of the trace and equal to the length of the bond pads. The copper pillars are mounted to the traces with solder joints.

摘要翻译： 电子部件封装包括具有上表面的基板。 基板的上表面上的痕迹沿纵向方向延伸。 迹线在纬度方向上具有第一纬向宽度，纬度方向垂直于纵向方向。 矩形铜柱连接到电子部件的接合焊盘，铜柱具有纵向长度和纬向第二宽度。 铜柱的纬向第二宽度等于并与轨迹的第一纬度宽度对齐。 此外，铜柱的纵向长度与迹线的纵向平行，并且等于接合焊盘的长度。 铜柱用焊点安装到轨迹上。

公开(公告)号：US08482134B1

公开(公告)日：2013-07-09

申请号：US12917185

申请日：2010-11-01

申请人： Robert Francis Darveaux ,  Roger D. St. Amand ,  Vladimir Perelman

发明人： Robert Francis Darveaux ,  Roger D. St. Amand ,  Vladimir Perelman

IPC分类号： H01L23/488

CPC分类号： H01L23/49816 ,  H01L21/50 ,  H01L23/36 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A stackable package is placed within a mold during an encapsulation operation. A compliant surface, e.g., of a compliant film, of the mold is pressed down on upper interconnection balls of the stackable package to force upper portions of the upper interconnection balls into the mold. However, lower portions of the upper interconnection balls are exposed within a space between the compliant surface and a substrate of the stackable package. The space is filled with a dielectric material to form a package body. The package body is formed while at the same time exposing the upper portions of upper interconnection balls from the package body in a single encapsulation operation. By avoiding selective removal of the package body to expose the upper interconnection balls, the number of operations as well as cost to manufacture the stackable package is minimized.

摘要翻译： 在封装操作期间，将可堆叠的封装放置在模具内。 模具的顺应性表面（例如柔顺膜）的柔顺表面被压在可堆叠包装的上互连球上，以将上互连球的上部部分压入模具中。 然而，上互连球的下部暴露在顺应性表面和可堆叠包装的基底之间的空间内。 空间填充有电介质材料以形成封装体。 同时，在单个封装操作中同时形成封装主体，同时将上互连球的上部从封装主体露出。 通过避免选择性地去除封装体以暴露上互连球，操作的数量以及制造可堆叠封装的成本最小化。

公开(公告)号：US08390116B1

公开(公告)日：2013-03-05

申请号：US13065298

申请日：2011-03-18

申请人： Ronald Patrick Huemoeller ,  Roger D. St. Amand ,  Robert Francis Darveaux

发明人： Ronald Patrick Huemoeller ,  Roger D. St. Amand ,  Robert Francis Darveaux

IPC分类号： H01L23/48

CPC分类号： H01L21/4853 ,  H01L24/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14

摘要： A method includes forming a patterned buildup layer on a first surface of a dielectric layer, the patterned buildup layer including a patterned buildup layer opening exposing a trace coupled to the dielectric layer. A conductor layer is flash plated on the patterned buildup layer and within the patterned buildup layer opening. The patterned buildup layer opening is filled with a blanket conductive filler layer. The blanket conductive filler layer and the conductor layer are planarized to form a flip chip bump.

摘要翻译： 一种方法包括在电介质层的第一表面上形成图案化的聚集层，所述图案化的构建层包括图案化的积层层，其暴露耦合到电介质层的迹线。 导体层被闪镀在图案化的积层和图案化的积层层开口内。 图案化的积层层开口填充有覆盖层导电填料层。 将覆盖层导电填料层和导体层平坦化以形成倒装芯片凸块。

公开(公告)号：US08300423B1

公开(公告)日：2012-10-30

申请号：US12787238

申请日：2010-05-25

申请人： Robert Francis Darveaux ,  Ludovico Bancod ,  Akito Yoshida

发明人： Robert Francis Darveaux ,  Ludovico Bancod ,  Akito Yoshida

IPC分类号： H01R9/00 ,  H01K1/18

CPC分类号： H01L25/105 ,  H01L23/5389 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014

摘要： A method of forming a stackable treated via package includes coupling interconnection balls to terminals. The interconnection balls are encapsulated in a package body. Via apertures are formed in the package body to expose the interconnection balls. The interconnection balls are treated to form treated interconnection balls comprising treated surfaces. The treated interconnection balls of the stackable treated via package enhance bonding with interconnection balls of a stacked electronic component package thus maximizing yield.

摘要翻译： 形成可堆叠处理的通孔封装的方法包括将互连球耦合到端子。 互连球被封装在封装体内。 在封装体中形成通孔，以露出互连球。 对互连球进行处理，以形成包括处理过的表面的经处理的互连球。 可堆叠处理的通孔封装的经处理的互连球增强了与堆叠的电子部件封装的互连球的粘合，从而使产量最大化。

公开(公告)号：US07898093B1

公开(公告)日：2011-03-01

申请号：US11592889

申请日：2006-11-02

申请人： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

发明人： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

IPC分类号： H01L23/28

CPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105

摘要： An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

摘要翻译： 曝光的芯片包覆成型的倒装芯片封装包括衬底。 芯片安装在基板的上表面上。 该包装还包括填充模具的活性表面和基材的上表面之间的空间的模具盖。 模具帽包括主表面，从基板的上表面延伸到主表面的侧壁，与模具的非活性表面共面并从模具的非活性表面的外围边缘向外延伸的环形表面，并且突出 表面在主表面和环形表面之间延伸。 模具盖不覆盖模具的非活性表面，使得从模具到周围环境的热传递最大化并且封装厚度最小化。

公开(公告)号：US08337657B1

公开(公告)日：2012-12-25

申请号：US12913325

申请日：2010-10-27

申请人： Brett Arnold Dunlap ,  Robert Francis Darveaux

发明人： Brett Arnold Dunlap ,  Robert Francis Darveaux

IPC分类号： B29C65/50 ,  B32B37/26 ,  B32B38/10

CPC分类号： H01L23/28 ,  B32B7/06 ,  C09J7/00 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/48 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68381 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10T156/11 ,  Y10T156/1168 ,  Y10T156/1189 ,  Y10T428/1481 ,  Y10T428/1495 ,  Y10T428/24942 ,  Y10T428/31504 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of fabricating a plurality of electronic component packages includes coupling a tape to a panel. Electronic components are coupled to the tape and encapsulated to form a molded wafer. The molded wafer is mechanically separated from the panel without heating by breaking a mechanical separation adhesive of the tape. By mechanically separating the molded wafer from the panel without heating, warpage of the molded wafer associated with heating is avoided.

摘要翻译： 制造多个电子部件封装的方法包括将带连接到面板。 电子部件耦合到带并被封装以形成模制的晶片。 通过破坏带的机械分离粘合剂，将模制的晶片与板材机械分离而不加热。 通过将模制的晶片与板的机械分离而不加热，避免了与加热相关联的模制晶片的翘曲。