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公开(公告)号：US09881677B1
公开(公告)日：2018-01-30
申请号：US15498369
申请日：2017-04-26
Applicant: MACRONIX International Co., Ltd.
Inventor： Ji-Yu Hung , Kai-Hsiang Chiang
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3418
Abstract: A sensing amplifier includes a first bit line driver, a second bit line driver and a third bit line driver. The first bit line driver sets a first bit line for a fast-pass-write (FPW) operation. The second bit line driver sets a second bit line for a first operation rather than the FPW operation. The third bit line driver sets a third bit line for a second operation rather than the FPW operation. The first bit line is arranged between the second bit line and the third bit line, and the second bit line driver and the third bit line driver respectively adjust voltage statuses of the second bit line and the third bit line to rise a voltage level of the first bit line by a compensated level.
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公开(公告)号：US20140254260A1
公开(公告)日：2014-09-11
申请号：US13946123
申请日：2013-07-19
Applicant: Macronix International Co., Ltd.
Inventor： Shuo-Nan Hung , Ji-Yu Hung
IPC: G11C16/26
Abstract: A method is provided for sensing data in a memory device. The memory device includes a block of memory cells coupled to a plurality of bit lines. The method includes precharging the plurality of bit lines to a first level VPRE. The method includes enabling current flow through selected memory cells on the plurality of bit lines to a reference line or to reference lines coupled to a reference voltage. The method includes preventing a voltage change as a result of the current flow on the bit lines from causing a bit line voltage to pass outside a range between the first level and a second level VKEEP, where the second level is lower than the first level and higher than the reference voltage. The method includes sensing data in the selected memory cells.
Abstract translation: 提供了一种用于感测存储器件中的数据的方法。 存储器件包括耦合到多个位线的存储器单元块。 该方法包括将多个位线预充电到第一级VPRE。 该方法包括实现电流流过多条位线上的选定存储单元到参考线或耦合到参考电压的参考线。 该方法包括防止由于位线上的电流而导致的电压变化导致位线电压超出第一电平和第二电平VKEEP之间的范围，其中第二电平低于第一电平， 高于参考电压。 该方法包括感测所选存储单元中的数据。
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公开(公告)号：US12272406B2
公开(公告)日：2025-04-08
申请号：US18150594
申请日：2023-01-05
Applicant: Macronix International Co., Ltd.
Inventor： E-Yuan Chang , Ji-Yu Hung
Abstract: A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.
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公开(公告)号：US11217313B2
公开(公告)日：2022-01-04
申请号：US17107692
申请日：2020-11-30
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ji-Yu Hung
Abstract: The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node.
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公开(公告)号：US10885986B2
公开(公告)日：2021-01-05
申请号：US16278026
申请日：2019-02-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ji-Yu Hung
Abstract: The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node.
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Patent Agency Ranking
公开(公告)号：US09887011B1
公开(公告)日：2018-02-06
申请号：US15425363
申请日：2017-02-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ji-Yu Hung
CPC classification number: G11C16/24 , G11C11/565 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C2207/002
Abstract: A memory device includes a memory array and bit lines coupled to the memory array. A voltage source is included for supplying a voltage used during a charging operation. Bit line clamp transistors, such as bit line clamp transistors, are coupled to the voltage source, and configured to regulate current on the corresponding bit lines in response to a bit line control signal. A control circuit generates the bit line control signal in response to a feedback signal. A feedback circuit is provided that is coupled to the voltage source and produces the feedback signal. The feedback circuit senses load of the bit lines being charged. The load of the bit lines being charged can be sensed by sensing the magnitude of the current from the voltage source during the charging operation.
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公开(公告)号：US20140313830A1
公开(公告)日：2014-10-23
申请号：US14319457
申请日：2014-06-30
Applicant: Macronix International Co., Ltd.
Inventor： Ji-Yu Hung
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3418
Abstract: A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.
Abstract translation: 页缓冲电路耦合到存储器阵列的位线。 页面缓冲电路包括在多阶段程序操作的不同阶段存储不同数据的锁存器。 准备阶段是在程序阶段之后和程序验证阶段之后的当前多阶段程序操作。 对于准备阶段，控制电路使锁存器存储指示在本多阶段程序操作之后的随后的多相程序操作中是否对存储单元进行编程的准备数据。 程序验证阶段的结果以及当前多阶段程序操作开始时的锁存器的内容足以确定准备数据。
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公开(公告)号：US12131787B2
公开(公告)日：2024-10-29
申请号：US17891589
申请日：2022-08-19
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shuo-Nan Hung , E-Yuan Chang , Ji-Yu Hung
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/24 , H03K19/20
Abstract: A memory such as a 3D NAND array, having a page buffer having page buffer cells coupled to bit lines has a search word input such as a search word buffer coupled to word lines. A circuit, such as string select gates, is provided to connect a selected set of memory cells in the array to the page buffer. The page buffer includes sensing circuitry configured to apply a match sense signal to a latch in a plurality of storage elements for a stored data word and an input search word. Logic circuitry uses storage elements in the plurality of storage elements of the page buffer to accumulate the match sense signals output by the sensing circuitry over a sequence matching a plurality stored data words to one or more input search words. A match for a search is based on a threshold and the accumulated match sense signals.
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公开(公告)号：US20240194228A1
公开(公告)日：2024-06-13
申请号：US18077557
申请日：2022-12-08
Applicant: Macronix International Co., Ltd.
Inventor： Ji-Yu Hung , E-Yuan Chang
CPC classification number: G11C7/1048 , G11C16/30
Abstract: Systems, methods, circuits, and apparatus for managing data transfer in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first circuit, a data bus coupled to the first circuit, and a precharging circuit coupled to the data bus. The precharging circuit is configured to precharge the data bus to have a predetermined voltage before data is transferred through the data bus. The first circuit is conductively coupled to the data bus by applying a control voltage to the first circuit. The control voltage is determined based on the predetermined voltage.
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公开(公告)号：US10957384B1
公开(公告)日：2021-03-23
申请号：US16581562
申请日：2019-09-24
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ji-Yu Hung , Shuo-Nan Hung
IPC: G11C16/06 , G11C11/4094 , G11C29/00 , G11C29/42 , G11C11/4093
Abstract: A memory device such as a page mode NAND flash, including a page buffer with first and second-level buffer latches is operated using a first pipeline stage, to transfer a page to the first-level buffer latches; a second pipeline stage, to clear the second-level buffer latches to a third buffer level and transfer the page from the first-level buffer latches to the second-level buffer latches; and a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing a second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.
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