公开(公告)号：US09349746B1

公开(公告)日：2016-05-24

申请号：US14594768

申请日：2015-01-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ta-Hone Yang ,  Nan-Tsu Lian ,  An Chyi Wei ,  Sheng-Yuan Chang ,  Kuang-Chao Chen

IPC: H01L29/51 ,  H01L27/115 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/511 ,  H01L29/518

Abstract: Present example embodiments relate generally to methods for fabricating semiconductor devices comprising forming an initial stack of alternating insulative and conductive layers over a substrate, identifying a plurality of bit line locations and word line locations for the initial stack, including a first bit line location and a first word line location, and forming, from the initial stack, a vertical arrangement of bit lines in the first bit line location, the vertical arrangement of bit lines having opposing sidewalls. The method further comprises forming a word line by forming a thin conductive layer over selected sections of the opposing sidewalls, the selected sections of the opposing sidewalls being sections within the first word line location. The forming the word line further comprises depositing conductive material adjacent to each thin conductive layer, the deposited conductive material in direct contact with the thin conductive layer.

Abstract translation: 本示例实施例一般涉及用于制造半导体器件的方法，包括在衬底上形成交替的绝缘和导电层的初始叠层，识别用于初始堆叠的多个位线位置和字线位置，包括第一位线位置和 第一字线位置，并且从初始堆叠形成第一位线位置中的位线的垂直布置，位线的垂直布置具有相对的侧壁。 该方法还包括通过在相对侧壁的选定部分上形成薄导电层来形成字线，相对侧壁的选定部分是第一字线位置内的部分。 形成字线还包括沉积与每个薄导电层相邻的导电材料，沉积的导电材料与薄导电层直接接触。

公开(公告)号：US20160110859A1

公开(公告)日：2016-04-21

申请号：US14516961

申请日：2014-10-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Hsiao-Leng Li ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06T7/00

CPC classification number: G06T7/001 ,  G06T7/12 ,  G06T2207/10056 ,  G06T2207/30148

Abstract: An inspection method for contact by die to database is provided. In the method, a plurality of raw images of contacts in a wafer is obtained, and a plurality of locations of the raw images is then recoded to obtain a graphic file. After that, the graphic file is aligned on a design database of the chip. An image extraction is then performed on the raw images to obtain a plurality of image contours of the contacts. Thereafter, a difference in critical dimension between the image contours of the contacts and corresponding contacts in the design database are measured in order to obtain the inspection result for contacts in the wafer.

Abstract translation: 提供了一种用于与数据库接触的检查方法。 在该方法中，获得晶片中的接触的多个原始图像，然后重新编码原始图像的多个位置以获得图形文件。 之后，图形文件在芯片的设计数据库上对齐。 然后对原始图像执行图像提取以获得联系人的多个图像轮廓。 此后，为了获得晶片中的触点的检查结果，测量了触点的图像轮廓与设计数据库中的对应触点之间的临界尺寸差异。

公开(公告)号：US09305794B2

公开(公告)日：2016-04-05

申请号：US14246527

申请日：2014-04-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Ta-Hone Yang

IPC: H01L21/30 ,  H01L21/306 ,  C09K13/00 ,  C09K13/02 ,  C09K13/04 ,  C09K13/06 ,  C09K13/08 ,  C23F1/10 ,  C23F1/12

CPC classification number: H01L21/30604 ,  C09K13/00 ,  C09K13/02 ,  C09K13/04 ,  C09K13/06 ,  C09K13/08 ,  C23F1/10 ,  C23F1/12 ,  H01L21/3065

Abstract: An etching method is disclosed. A substrate is provided. An etching is performed to form at least one opening in the substrate. An auxiliary etching layer is formed in the opening to cover at least one etching residue. The auxiliary etching layer includes a media, a carrier and an etching component encapsulated by the carrier. A treatment process is performed to the auxiliary etching layer. The treatment process includes applying an energy to the auxiliary etching layer or exposing the auxiliary layer to a gas, so that the carrier breaks in the treatment and thereby the etching component is released to etch the etching residue.

Abstract translation: 公开了蚀刻方法。 提供基板。 进行蚀刻以在衬底中形成至少一个开口。 在开口中形成辅助蚀刻层以覆盖至少一个蚀刻残留物。 辅助蚀刻层包括由载体封装的介质，载体和蚀刻部件。 对辅助蚀刻层进行处理工艺。 处理过程包括向辅助蚀刻层施加能量或将辅助层暴露于气体，使得载体在处理中断裂，从而释放蚀刻部件以蚀刻蚀刻残留物。

公开(公告)号：US09006003B1

公开(公告)日：2015-04-14

申请号：US14220993

申请日：2014-03-20

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Chi-Min Chen ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: H01L21/00 ,  G11C99/00 ,  H01L21/66 ,  G01R31/28

CPC classification number: H01L22/14 ,  G01R31/2851 ,  G06T7/0004 ,  G06T2207/10061 ,  G06T2207/30148 ,  G11C29/006 ,  G11C29/56008 ,  G11C2029/5604

Abstract: A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in each of layers within a wafer and a plurality of physical coordinates of the defects. Thereafter, a bitmap failure detection is performed to obtain digital coordinates of failure bits within the wafer. The digital coordinates are converted into a plurality of physical locations, and the physical locations are overlapped with the physical coordinates so as to rapidly obtain correlations between the failure bits and the defects.

Abstract translation: 提供了一种检测与物理坐标相关联的位图故障的方法。 在该方法中，首先获得晶片映射检查的数据，并且数据包括晶片内的每个层中的缺陷图像和缺陷的多个物理坐标。 此后，执行位图故障检测以获得晶片内的故障位的数字坐标。 数字坐标被转换成多个物理位置，并且物理位置与物理坐标重叠，以便快速获得故障位与缺陷之间的相关性。

公开(公告)号：US09869712B2

公开(公告)日：2018-01-16

申请号：US14694017

申请日：2015-04-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  I-Jen Huang ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06F17/50 ,  G01R31/28 ,  G01R31/265

CPC classification number: G01R31/2831 ,  G01R31/2653

Abstract: A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.

公开(公告)号：US20160358932A1

公开(公告)日：2016-12-08

申请号：US14730099

申请日：2015-06-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ta-Hone Yang

IPC: H01L27/115 ,  H01L21/768 ,  H01L29/51 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around vertical gate semiconductor structure comprising forming a plurality of layers over a substrate, the plurality of layers having alternating first insulative material layers and conductive material layers; identifying bit line and word line locations for the formation of bit lines and word lines; removing portions of the plurality of layers outside of the identified bit line and word line locations; forming vertical second insulative material structures in areas outside of the identified bit line and word line locations; removing portions of the plurality of layers in areas along the identified word line locations outside of the identified bit line locations; removing the first insulative material from the first insulative material layers in areas along the identified word line locations; forming bit lines in the identified bit line locations; and forming word lines in the identified word line locations.

Abstract translation: 本示例性实施例一般涉及制造三维栅极全周垂直栅极半导体结构的方法，包括在衬底上形成多个层，所述多个层具有交替的第一绝缘材料层和导电材料层; 识别用于形成位线和字线的位线和字线位置; 去除所识别的位线和字线位置之外的多个层的部分; 在所识别的位线和字线位置之外的区域中形成垂直的第二绝缘材料结构; 沿着所识别的位线位置之外的所识别的字线位置的区域中去除多个层中的部分; 在沿所识别的字线位置的区域中从所述第一绝缘材料层去除所述第一绝缘材料; 在所识别的位线位置中形成位线; 并在所识别的字线位置中形成字线。

公开(公告)号：US09244112B2

公开(公告)日：2016-01-26

申请号：US14275437

申请日：2014-05-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsiang-Chou Liao ,  Tuung Luoh ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: H01L21/66 ,  G01R31/04 ,  H01J37/22 ,  H01J37/244 ,  H01J37/28 ,  G01R31/305

CPC classification number: G01R31/04 ,  G01R31/305 ,  H01J37/222 ,  H01J37/244 ,  H01J37/28 ,  H01J2237/049 ,  H01J2237/063 ,  H01J2237/221 ,  H01J2237/24592 ,  H01J2237/2594 ,  H01J2237/28 ,  H01J2237/2817 ,  H01L22/12 ,  H01L22/14

Abstract: A method for detecting an electrical defect of contact/via plugs is provided. In the method, the contact/via plugs are monitored by an electron-beam (E-Beam) inspection tool to capture an image with a VC (voltage contrast) difference, and then an image extraction is performed on the image with the VC difference, wherein the image extraction is based on Target gray level/back ground gray level. The extracted image is contrasted with a layout design base to obtain a blind contact or Quasi-blind issue of contact/via plugs. A grayscale value of the VC difference having the blind contact or Quasi-blind issue is compared with a determined range of grayscale value to determine whether the VC difference is abnormal.

Abstract translation: 提供一种用于检测接触/通孔的电气缺陷的方法。 在该方法中，通过电子束（E-Beam）检查工具来监视接触/通孔塞以捕获具有VC（电压对比度）差异的图像，然后对具有VC差异的图像执行图像提取 ，其中所述图像提取基于目标灰度/背景灰度级。 提取的图像与布局设计基础形成对照，以获得接触/通孔插头的盲接或准盲问题。 将具有盲接或准盲问题的VC差的灰阶值与确定的灰度值范围进行比较，以确定VC差异是否异常。

公开(公告)号：US20150287608A1

公开(公告)日：2015-10-08

申请号：US14246527

申请日：2014-04-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Ta-Hone Yang

IPC: H01L21/306 ,  C09K13/04 ,  C23F1/12 ,  C09K13/02 ,  C09K13/00 ,  C23F1/10 ,  C09K13/08 ,  C09K13/06

CPC classification number: H01L21/30604 ,  C09K13/00 ,  C09K13/02 ,  C09K13/04 ,  C09K13/06 ,  C09K13/08 ,  C23F1/10 ,  C23F1/12 ,  H01L21/3065

Abstract: An etching method is disclosed. A substrate is provided. An etching is performed to form at least one opening in the substrate. An auxiliary etching layer is formed in the opening to cover at least one etching residue. The auxiliary etching layer includes a media, a carrier and an etching component encapsulated by the carrier. A treatment process is performed to the auxiliary etching layer. The treatment process includes applying an energy to the auxiliary etching layer or exposing the auxiliary layer to a gas, so that the carrier breaks in the treatment and thereby the etching component is released to etch the etching residue.

Abstract translation: 公开了蚀刻方法。 提供基板。 进行蚀刻以在衬底中形成至少一个开口。 在开口中形成辅助蚀刻层以覆盖至少一个蚀刻残留物。 辅助蚀刻层包括由载体封装的介质，载体和蚀刻部件。 对辅助蚀刻层进行处理工艺。 处理过程包括向辅助蚀刻层施加能量或将辅助层暴露于气体，使得载体在处理中断裂，从而释放蚀刻部件以蚀刻蚀刻残留物。

公开(公告)号：US09589086B2

公开(公告)日：2017-03-07

申请号：US14165043

申请日：2014-01-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Hsiang-Chou Liao ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06F17/00 ,  G06F17/50 ,  G02B21/00 ,  H01J37/28

CPC classification number: G06F17/5045 ,  G02B21/002 ,  H01J37/28 ,  H01J2237/221 ,  H01J2237/2817

Abstract: A method for measuring a surface structure of a chip or a wafer is provided that includes obtaining an image of the surface structure of the chip, and then performing an image extraction on the image to convert the extracted image into a first circuit design file. A standard image is selected to convert into a second circuit design file, and then the standard image and at least one target in the image are compared to obtain a difference therebetween. According to the difference, at least one data of the surface structure may be made, wherein the data is selected from one of line edge roughness (LER), line width roughness (LWR), contact edge roughness (CER), critical dimension (CD), bias, 3 sigma, maximum, minimum, etc. and repeating defect.

Abstract translation: 提供了一种用于测量芯片或晶片的表面结构的方法，其包括获得芯片的表面结构的图像，然后对图像执行图像提取以将提取的图像转换为第一电路设计文件。 选择标准图像以转换为第二电路设计文件，然后比较图像中的标准图像和至少一个目标，以获得它们之间的差异。 根据差异，可以进行表面结构的至少一个数据，其中数据从线边缘粗糙度（LER），线宽粗糙度（LWR），接触边缘粗糙度（CER），临界尺寸（CD） ），偏置，3西格玛，最大值，最小值等，并重复缺陷。

公开(公告)号：US20160314237A1

公开(公告)日：2016-10-27

申请号：US14694017

申请日：2015-04-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  I-Jen Huang ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06F17/50

CPC classification number: G01R31/2831 ,  G01R31/2653

Abstract: A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.

Abstract translation: 介绍了通过晶片排序检测晶片缺陷的方法。 在该方法中，使用晶片分类测试装置来获得DTL或ADART结果，其中晶片中的多个修复位置根据DTL或ADART结果被突出显示。 然后输出修复站点的多个物理位置。 分析设备用于将物理位置与晶片的图形数据系统（GDS）设计布局坐标进行匹配，以产生与修复位置的缺陷相关的数据。