公开(公告)号：US09847339B2

公开(公告)日：2017-12-19

申请号：US15096560

申请日：2016-04-12

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Min Hung ,  Chien-Ying Lee ,  Tzung-Ting Han

IPC: H01L21/768 ,  H01L27/11521 ,  H01L23/528 ,  H01L29/788 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L27/11521 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L28/00 ,  H01L29/7883

Abstract: Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.

公开(公告)号：US20160020216A1

公开(公告)日：2016-01-21

申请号：US14333893

申请日：2014-07-17

Applicant: Macronix International Co., Ltd.

Inventor： Shang-Wei Lin ,  Yu-Wei Hsu ,  Yu-Min Hung ,  Tzung-Ting Han

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

Abstract: A memory device is provided having a plurality of floating gates and control gates, which at least one control gate has been removed after applying a flowable material to the semiconductor which prevents damage to the substrate when the control gate is removed. Methods of manufacturing such a memory device are also provided.

Abstract translation: 提供具有多个浮动栅极和控制栅极的存储器件，在将可流动材料施加到半导体之后，至少一个控制栅极被去除，这防止了在控制栅极被去除时损坏衬底。 还提供了制造这种存储器件的方法。

公开(公告)号：US10290543B1

公开(公告)日：2019-05-14

申请号：US15848986

申请日：2017-12-20

Applicant: MACRONIX International Co., Ltd.

Inventor： Chang-Wen Jian ,  Hsiang-Lu Wu ,  Yu-Min Hung ,  Tzung-Ting Han

IPC: H01L49/02 ,  H01L21/768 ,  H01L21/3213

Abstract: A method for manufacturing semiconductor device is provided. A substrate having a memory region and a capacitance region is provided. A plurality of word line structures are formed on the memory region of the substrate. A capacitance structure is formed on the capacitance region of the substrate. The word line structures and the capacitance structure each include a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer, a second dielectric layer on the first conductive layer, and a second conductive layer on the second dielectric layer. The second conductive layers of the word line structures close to an edge of the memory region and a portion of the second conductive layer of the capacitance structure are removed at the same time to form a trench exposing a portion of the second dielectric layer.

公开(公告)号：US09553047B2

公开(公告)日：2017-01-24

申请号：US14735790

申请日：2015-06-10

Applicant: Macronix International Co. Ltd.

Inventor： Yu-Min Hung ,  Tzung-Ting Han ,  Miao-Chih Hsu

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/112

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/28273 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76892 ,  H01L27/11293 ,  H01L27/11519

Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the patterning of the array and periphery regions in self-aligned quadruple patterning and provide semiconductor devices resulting from the combined patterning.

Abstract translation: 提供了用于制造这种半导体存储器件的改进的半导体存储器件和方法。 一种方法可以结合阵列和外围区域的图案化，以自对准的四重图案化，并提供由组合图案化产生的半导体器件。

公开(公告)号：US20170294442A1

公开(公告)日：2017-10-12

申请号：US15096560

申请日：2016-04-12

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Min Hung ,  Chien-Ying Lee ,  Tzung-Ting Han

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L28/00 ,  H01L29/7883

Abstract: Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.