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1.发明授权Method and apparatus for improved performance of iterative decoders on channels with memory 有权用于改善具有存储器的通道上的迭代解码器性能的方法和装置公开(公告)号：US09438276B2
公开(公告)日：2016-09-06
申请号：US13674767
申请日：2012-11-12
发明人： Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
CPC分类号： H03M13/6331 , H03M13/1105 , H03M13/2957 , H03M13/3905 , H03M13/4138
摘要： Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.
摘要翻译： 公开了用于改善具有存储器的各种通道上的迭代解码器的性能的系统和方法。 这些系统和方法可以减少迭代解码器不能产生与最初在通信或数据存储系统中发送的数据匹配的解码数据的情况的频率或数量。 迭代解码器包括SISO信道检测器和ECC解码器，并且按照常规解码模式中的至少一个迭代解码算法和/或错误恢复模式中的至少一个迭代解码算法解码编码信息。
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公开(公告)号：US09081505B1
公开(公告)日：2015-07-14
申请号：US14261706
申请日：2014-04-25
发明人： Zining Wu
CPC分类号： G06F3/0619 , G06F3/061 , G06F3/064 , G06F3/0655 , G06F3/0656 , G06F3/0661 , G06F3/0674 , G06F3/0676
摘要： A method of writing data to a storage device that uses a first data block size, from a host system that uses a second data block size, different from the first data block size, includes receiving a request from the host system to write a host data block to the storage device, reading a storage device data block from a first location on the storage device to a buffer, where the storage device data block corresponds to the host data block, modifying the storage device data block based on the host data block, restricting writing of the modified storage device data block into the first location, and storing the modified storage device data block to a second location, different from the restricted first location. After acknowledging success of the storing, the restricting of writing of the modified storage device data block into the first location may be lifted.
摘要翻译： 从与第一数据块大小不同的使用第二数据块大小的主机系统向使用第一数据块大小的存储设备写入数据的方法包括从主机系统接收写入主机数据的请求 将存储设备数据块从存储设备上的第一位置读取到缓冲器，其中存储设备数据块对应于主机数据块，基于主机数据块修改存储设备数据块， 限制将修改的存储设备数据块写入第一位置，并将修改的存储设备数据块存储到与受限制的第一位置不同的第二位置。 在确认存储成功之后，可以解除将修改的存储设备数据块写入第一位置的限制。
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3.发明授权System and method for adding a drive to a storage system having multiple drives 有权将驱动器添加到具有多个驱动器的存储系统的系统和方法公开(公告)号：US09075745B1
公开(公告)日：2015-07-07
申请号：US13777538
申请日：2013-02-26
发明人： Heng Tang , Zining Wu , Gregory Burd , Pantas Sutardja
CPC分类号： G06F11/1076 , G06F11/08 , G06F11/1443 , G11C29/00 , H03M13/09 , H03M13/1515 , H03M13/155 , H03M13/611 , H03M13/618
摘要： A control module includes an encoder module, a detector module, a mapping module, and a difference module. The encoder module receives data, and based on the data, generates a first code word for drives. The drives are associated with a storage system. The detector module detects an addition of a second drive. The encoder module generates a second code word for the second drive. The mapping module: maps physical locations of the data in the drives to logical locations of the first code word; assigns a predetermined value to a logical location corresponding to an unused logical location; and based on the predetermined value, assigns the unused logical location to the second drive. The difference module generates a third code word based on each of the first and second code words. The encoder module, based on the first and third code words, generates a fourth code word for all drives.
摘要翻译： 控制模块包括编码器模块，检测器模块，映射模块和差分模块。 编码器模块接收数据，并根据该数据生成驱动器的第一代码字。 驱动器与存储系统相关联。 检测器模块检测到第二个驱动器的添加。 编码器模块为第二个驱动器生成第二个代码字。 映射模块：将驱动器中的数据的物理位置映射到第一个代码字的逻辑位置; 向与未使用的逻辑位置相对应的逻辑位置分配预定值; 并且基于预定值，将未使用的逻辑位置分配给第二驱动器。 差分模块基于第一和第二代码字中的每一个生成第三代码字。 编码器模块基于第一和第三代码字，为所有驱动器生成第四代码字。
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4.发明授权Method and apparatus for controlling a number of decoding iterations of a decoder based on a temperature of an integrated circuit that includes the decoder 有权用于基于包括解码器的集成电路的温度来控制解码器的解码迭代次数的方法和装置公开(公告)号：US09071280B1
公开(公告)日：2015-06-30
申请号：US14518461
申请日：2014-10-20
发明人： Hongying Sheng , Zining Wu
CPC分类号： H03M13/2909 , H03M13/1111 , H03M13/1128 , H03M13/2948 , H03M13/2957 , H03M13/3753 , H03M13/3905 , H03M13/41 , H03M13/6331 , H03M13/6343 , H04L1/005 , H04L1/0051 , H04L1/0053
摘要： An integrated circuit including a first decoder, a second decoder, a sensor, and a controller. The first decoder generates first data by performing a first number of decoding iterations and generates second data after performing all of the first number of decoding iterations. The second decoder performs a second number of decoding iterations and generates soft information based on input samples and/or the second data. Each of the second number of decoding iterations is performed after all of the first number of decoding iterations. The first decoder generates the first data based on the soft information and/or the first data from one of the first number of decoding iterations. The sensor senses a temperature of the integrated circuit. The controller controls, based on the temperature of the integrated circuit, at least one of the first number of decoding iterations or the second number of decoding iterations.
摘要翻译： 一种集成电路，包括第一解码器，第二解码器，传感器和控制器。 第一解码器通过执行第一数量的解码迭代来生成第一数据，并且在执行所有第一数量的解码迭代之后产生第二数据。 第二解码器执行第二数量的解码迭代，并且基于输入样本和/或第二数据生成软信息。 第二数量的解码迭代中的每一个在所有第一数量的解码迭代之后被执行。 第一解码器基于来自第一数量的解码迭代之一的软信息和/或第一数据生成第一数据。 传感器感测集成电路的温度。 控制器基于集成电路的温度来控制第一数量的解码迭代或第二数量的解码迭代中的至少一个。
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5.发明授权Channel decoder and method for generating equalized data and data estimates based on multiple sets of depths provided via a viterbi algorithm 有权用于基于通过维特比算法提供的多组深度产生均衡数据和数据估计的信道解码器和方法公开(公告)号：US09026894B1
公开(公告)日：2015-05-05
申请号：US13854510
申请日：2013-04-01
发明人： Hongwei Song , Zining Wu
CPC分类号： G11B20/1866 , G11B20/10009 , G11B20/10027 , G11B20/10037 , G11B20/10203 , G11B20/10361 , G11B20/1833 , G11B2220/2516 , H03M13/3746 , H03M13/41 , H03M13/6343 , H04L1/0047 , H04L1/0054 , H04L25/067
摘要： A channel decoder includes a demodulator, a filter, a detector module, and first and second circuits. The demodulator receives an input signal based on data read from a storage medium, and demodulates the input signal to generate a data signal. The filter generates equalized data based on the data signal. The detector module executes a Viterbi algorithm based on the equalized data to generate estimates of data originally stored in the storage medium, and based on the execution of the Viterbi algorithm, generates a first and second sets of depths. The first set of depths includes depths larger than depths in the second set of depths. The first circuit generates a first error signal based on the first set of depths. The second circuit generates a second error signal based on the second set of depths. The filter generates the equalized data based on the first and second error signals.
摘要翻译： 信道解码器包括解调器，滤波器，检测器模块以及第一和第二电路。 解调器基于从存储介质读取的数据接收输入信号，并解调输入信号以产生数据信号。 滤波器基于数据信号产生均衡的数据。 检测器模块基于均衡数据执行维特比算法，以产生原始存储在存储介质中的数据的估计，并且基于维特比算法的执行，生成第一和第二深度集合。 第一组深度包括比第二组深度深度大的深度。 第一电路基于第一组深度产生第一误差信号。 第二电路基于第二组深度产生第二误差信号。 滤波器基于第一和第二误差信号产生均衡数据。
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公开(公告)号：US08819530B1
公开(公告)日：2014-08-26
申请号：US13973880
申请日：2013-08-22
发明人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： H03M13/03
CPC分类号： H03M13/1117 , H03M13/114 , H03M13/116 , H03M13/2957 , H03M13/4138 , H03M13/6325 , H03M13/6343 , H03M13/6561
摘要： The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes R banks; Q banks; circuitry configured to store R data for a current codeword in a first R bank of the R banks and store R data for a previous codeword in a second R bank of the R banks; circuitry configured to alternate among the R banks for storing current codeword R data; circuitry configured to store Q data for the current codeword in a first Q bank of the Q banks and store Q data for the previous codeword in a second Q bank of the Q banks; and circuitry configured to alternate among the Q banks for storing current codeword Q data. The apparatus can include circuitry configured to interleave read accesses among the R banks.
摘要翻译： 本公开包括与迭代解码器存储器布置相关的装置，系统和技术。 所描述的装置包括R组; Q银行 配置为存储当前码字的R数据在R组的第一R组中的R数据并存储在R组的第二R组中的先前码字的R数据; 配置为在R组之间交替存储当前码字R数据的电路; 电路，被配置为存储所述Q组的第一Q组中当前码字的Q数据，并存储所述Q组的第二Q组中的所述先前码字的Q数据; 以及被配置为在Q组之间交替存储当前码字Q数据的电路。 该装置可以包括被配置为在R组之间交错读取访问的电路。
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公开(公告)号：US08819500B1
公开(公告)日：2014-08-26
申请号：US14047491
申请日：2013-10-07
发明人： Shaohua Yang , Zining Wu
CPC分类号： G06F11/0751 , G11B20/1816 , G11B2020/1823 , G11B2220/2504 , G11B2220/2516 , G11B2220/2562
摘要： A system including a reconstruction module and a correlation module. The reconstruction module is configured to reconstruct data bits detected from first signals, and to generate second signals based on the reconstruction of the data bits detected from the first signals. The correlation module is configured to generate first correlation values by correlating (i) the first signals and (ii) the second signals, and to generate second correlation values by self-correlating the second signals. In response to one or more of (i) the first signals and (ii) the second signals including a floating number having (i) a plurality of bits and (ii) a sign bit, the correlation module is configured to generate one or more of (i) the first correlation values and (ii) the second correlation values based on (i) a plurality of most significant bits of the floating number and (ii) the sign bit of the floating number.
摘要翻译： 一种包括重建模块和相关模块的系统。 重建模块被配置为重建从第一信号检测到的数据位，并且基于从第一信号检测到的数据位的重建来生成第二信号。 相关模块被配置为通过将（i）第一信号和（ii）第二信号相关联来产生第一相关值，并且通过对第二信号进行自相关来产生第二相关值。 响应于（i）第一信号和（ii）第二信号中的一个或多个，包括具有（i）多个位和（ii）符号位的浮动数字的第二信号，相关模块被配置为产生一个或多个 （i）第一相关值和（ii）基于（i）浮动数的多个最高有效位和（ii）浮动数的符号位的第二相关值。
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公开(公告)号：US08743616B1
公开(公告)日：2014-06-03
申请号：US13747114
申请日：2013-01-22
发明人： Zining Wu , Xueshi Yang , Pantas Sutardja
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C2029/1202 , G11C2029/1204
摘要： A system including an interference module and a programming module. The interference module is configured to generate interference values based on (i) a state to which a memory cell is to be programmed and (ii) states of one or more memory cells located near the memory cell, and store the interference values. The interference values indicate effects of the states of the one or more memory cells on the state to which the memory cell is to be programmed. The programming module is configured to determine a programming value to program the memory cell to the state based on one or more of the interference values.
摘要翻译： 一种包括干扰模块和编程模块的系统。 干扰模块被配置为基于（i）要对存储器单元进行编程的状态和（ii）位于存储器单元附近的一个或多个存储单元的状态并且存储干扰值来产生干扰值。 干扰值表示一个或多个存储器单元的状态对存储器单元将被编程的状态的影响。 编程模块被配置为基于一个或多个干扰值来确定编程值以将存储器单元编程到状态。
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公开(公告)号：US09245632B1
公开(公告)日：2016-01-26
申请号：US14294457
申请日：2014-06-03
发明人： Zining Wu , Xueshi Yang , Pantas Sutardja
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C2029/1202 , G11C2029/1204
摘要： A system including an interference module and a programming module. The interference module is configured to generate interference values based on (i) a state to which a memory cell is to be programmed and (ii) states of one or more memory cells located near the memory cell. The interference values indicate effects of the states of the one or more memory cells on the state to which the memory cell is to be programmed. The programming module is configured to determine a programming value to program the memory cell to the state based on one or more of the interference values. The one or more of the interference values are selected based on (i) the state to which the memory cell is to be programmed, and (ii) the states of the one or more memory cells.
摘要翻译： 一种包括干扰模块和编程模块的系统。 干扰模块被配置为基于（i）要对存储器单元进行编程的状态和（ii）位于存储器单元附近的一个或多个存储单元的状态来产生干扰值。 干扰值表示一个或多个存储器单元的状态对存储器单元将被编程的状态的影响。 编程模块被配置为基于一个或多个干扰值来确定编程值以将存储器单元编程到状态。 基于（i）要对存储器单元进行编程的状态和（ii）一个或多个存储器单元的状态来选择一个或多个干扰值。
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公开(公告)号：US09009560B1
公开(公告)日：2015-04-14
申请号：US14309319
申请日：2014-06-19
发明人： Adina Matache , Heng Tang , Gregory Burd , Aditya Ramamoorthy , Jun Xu , Zining Wu
CPC分类号： H03M13/1177 , H03M13/116 , H03M13/1188
摘要： An apparatus includes a circuit configured to at least one of (i) encode first data to produce encoded data or (ii) decode second data to produce decoded data. The circuit is configured to operate according to a predetermined matrix. The predetermined matrix is represented by a two-dimensional grid of elements. Each element of the predetermined matrix labeled with a hyphen corresponds to a zero matrix. Each element of the predetermined matrix labeled with a number corresponds to a respective cyclic-permutation matrix.
摘要翻译： 一种装置包括被配置为（i）编码第一数据以产生编码数据或（ii）解码第二数据以产生解码数据中的至少一个的电路。 电路被配置为根据预定矩阵进行操作。 预定矩阵由元素的二维网格表示。 用连字符标记的预定矩阵的每个元素对应于零矩阵。 用数字标注的预定矩阵的每个元素对应于相应的循环置换矩阵。
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